DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 18, it depends on claim 1 and recites the limitation “the undoped semiconductor layer” and there is insufficient antecedent basis for this limitation in the claim. It appears claim 18 should depend on claim 17 instead of claim 1.
Clear explanation or claim modification is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-9 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Saito (US publication 2017/0069793 A1), hereinafter referred to as Saito793, in view of Chen et al. (US publication 2019/0334059 A1), hereinafter referred to as Chen059.
Regarding claim 1, Saito793 teaches a light-emitting element (fig. 1 and related text), including: a substrate (10, [0026]) including an upper surface (top surface); a plurality of protrusions formed on the upper surface (fig. 1); and a stack structure (13/14/15/16, [0026]) formed on the substrate, wherein the stack structure includes a first doped semiconductor layer (13, [0026]), a light-emitting layer (14, [0026]), and a second doped semiconductor layer (16, [0026]), wherein the stack structure includes a total thickness less than 4 μm (Saito793 teaches the thickness of a first doped semiconductor layer (13) is 0.5 μm to 3 μm ([0040], the thickness of the light-emitting layer (14) is less than 1 μm ([0044]), the thickness of the electron blocking layer (15) is 1 nm to 50 nm ([0046]), and the thickness of the second doped semiconductor layer (16) is about 50 nm ([0050]) and thus makes it obvious that wherein the stack structure includes a total thickness less than 4 μm (for a specific instance a combined thickness of 13/14/15/16 is less than 4 μm) and also is well-known in the art that a width/thickness of a semiconducting or insulation or conductive layer depends on a process technology, overall size of the device, and is a result-effective variable as electrical properties (conductivity, current, resistance, doping, insulation, withstanding breakdown, etc.) depend on the width/thickness of a semiconducting or insulation or conductive layer. So, a width/thickness of a semiconducting or insulation or conductive layer is a parameter that one must consider and decide upon and is something that can be optimized through routine experimentation and it has been held where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation (MPEP §2144.05 II/III)).
Saito793 does not explicitly teach wherein the plurality of protrusions includes a height less than or equal to 1 μm.
Chen059 teaches wherein the plurality of protrusions (102c, fig. 1a-1b) includes a height less than or equal to 1 μm ([0013]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Saito793 with that of Chen059 so that wherein the plurality of protrusions includes a height less than or equal to 1 μm so that the light-emitting device has a full width at half maximum (FWHM) of smaller than 250 arcsec in accordance with a (102) XRD rocking curve ([0004]).
Regarding claim 2, Saito793 teaches wherein the substrate includes a sapphire substrate ([0027]).
Regarding claim 3, Saito793 teaches wherein the plurality of protrusions includes a cone shape ([0028]. fig. 1).
Regarding claim 4, Chen059 teaches wherein the height is between 0.65 μm˜0.95 μm ([0013], fig. 1a-1b). Furthermore, it is well-known in the art that a width/thickness of a semiconducting or insulation or conductive layer depends on a process technology, overall size of the device, and is a result-effective variable as electrical properties (conductivity, current, resistance, doping, insulation, withstanding breakdown, etc.) depend on the width/thickness of a semiconducting or insulation or conductive layer. So, a width/thickness of a semiconducting or insulation or conductive layer is a parameter that one must consider and decide upon and is something that can be optimized through routine experimentation and it has been held where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. (MPEP §2144.05 II/III).
Regarding claim 5, Chen059 teaches wherein the plurality of protrusions includes a width between 0.6 μm˜1.6 μm ([0013], fig. 1a-1b). Furthermore, it is well-known in the art that a width/thickness of a semiconducting or insulation or conductive layer depends on a process technology, overall size of the device, and is a result-effective variable as electrical properties (conductivity, current, resistance, doping, insulation, withstanding breakdown, etc.) depend on the width/thickness of a semiconducting or insulation or conductive layer. So, a width/thickness of a semiconducting or insulation or conductive layer is a parameter that one must consider and decide upon and is something that can be optimized through routine experimentation and it has been held where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. (MPEP §2144.05 II/III).
Regarding claim 6, Chen059 teaches wherein the plurality of protrusions includes an aspect ratio between 0.55˜0.85 ([0013], fig. 1a-1b). Furthermore, it is well-known in the art that a width/thickness of a semiconducting or insulation or conductive layer depends on a process technology, overall size of the device, and is a result-effective variable as electrical properties (conductivity, current, resistance, doping, insulation, withstanding breakdown, etc.) depend on the width/thickness of a semiconducting or insulation or conductive layer. So, a width/thickness of a semiconducting or insulation or conductive layer is a parameter that one must consider and decide upon and is something that can be optimized through routine experimentation and it has been held where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. (MPEP §2144.05 II/III).
Regarding claim 7, Chen059 teaches wherein a distance between the plurality of protrusions is between 0.1 μm˜0.3 μm ([0013], fig. 1a-1b). Furthermore, it is well-known in the art that a width/thickness of a semiconducting or insulation or conductive layer depends on a process technology, overall size of the device, and is a result-effective variable as electrical properties (conductivity, current, resistance, doping, insulation, withstanding breakdown, etc.) depend on the width/thickness of a semiconducting or insulation or conductive layer. So, a width/thickness of a semiconducting or insulation or conductive layer is a parameter that one must consider and decide upon and is something that can be optimized through routine experimentation and it has been held where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. (MPEP §2144.05 II/III).
Regarding claim 8, Chen059 teaches wherein a distance between the plurality of protrusions is between 0.6 μm˜1.6 μm ([0013], fig. 1a-1b). Furthermore, it is well-known in the art that a width/thickness of a semiconducting or insulation or conductive layer depends on a process technology, overall size of the device, and is a result-effective variable as electrical properties (conductivity, current, resistance, doping, insulation, withstanding breakdown, etc.) depend on the width/thickness of a semiconducting or insulation or conductive layer. So, a width/thickness of a semiconducting or insulation or conductive layer is a parameter that one must consider and decide upon and is something that can be optimized through routine experimentation and it has been held where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. (MPEP §2144.05 II/III).
Regarding claim 9, Chen059 teaches wherein a ratio of an area of the substrate not occupied by the plurality of protrusions to an area of the plurality of protrusions is greater than 35% ([0013], fig. 1a-1b). Furthermore, it is well-known in the art that a width/thickness of a semiconducting or insulation or conductive layer depends on a process technology, overall size of the device, and is a result-effective variable as electrical properties (conductivity, current, resistance, doping, insulation, withstanding breakdown, etc.) depend on the width/thickness of a semiconducting or insulation or conductive layer. So, a width/thickness of a semiconducting or insulation or conductive layer is a parameter that one must consider and decide upon and is something that can be optimized through routine experimentation and it has been held where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. (MPEP §2144.05 II/III).
Regarding claim 16, Saito793 teaches wherein the stack structure further includes an undoped semiconductor layer (12, [0034]) formed between the substrate and the first doped semiconductor layer, and a thickness of the first doped semiconductor layer and a thickness of the undoped semiconductor layer include a ratio between 0.9˜1.1 (Saito793 teaches a thickness of a first doped semiconductor layer (13) is 0.5 μm to 3 μm ([0040]) and a thickness of the undoped semiconductor layer (12) is 0.5 μm to 10 μm ([0035] and thus makes it obvious that a thickness of the first doped semiconductor layer and a thickness of the undoped semiconductor layer include a ratio between 0.9˜1.1 and also is well-known in the art that a width/thickness of a semiconducting or insulation or conductive layer depends on a process technology, overall size of the device, and is a result-effective variable as electrical properties (conductivity, current, resistance, doping, insulation, withstanding breakdown, etc.) depend on the width/thickness of a semiconducting or insulation or conductive layer. So, a width/thickness of a semiconducting or insulation or conductive layer is a parameter that one must consider and decide upon and is something that can be optimized through routine experimentation and it has been held where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation (MPEP §2144.05 II/III))
Regarding claim 17, Saito793 teaches wherein the stack structure further includes an undoped semiconductor layer (12, [0034]) formed between the substrate and the first doped semiconductor layer (fig. 1), and the undoped semiconductor layer includes a thickness less than 2 μm ([0035]). Furthermore, it is well-known in the art that a width/thickness of a semiconducting or insulation or conductive layer depends on a process technology, overall size of the device, and is a result-effective variable as electrical properties (conductivity, current, resistance, doping, insulation, withstanding breakdown, etc.) depend on the width/thickness of a semiconducting or insulation or conductive layer. So, a width/thickness of a semiconducting or insulation or conductive layer is a parameter that one must consider and decide upon and is something that can be optimized through routine experimentation and it has been held where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. (MPEP §2144.05 II/III).
Regarding claim 18, Saito793 teaches wherein the undoped semiconductor layer includes a thickness 1.5 μm thicker than the height of the plurality of protrusions ([0032-0035], fig. 1). Furthermore, it is well-known in the art that a width/thickness of a semiconducting or insulation or conductive layer depends on a process technology, overall size of the device, and is a result-effective variable as electrical properties (conductivity, current, resistance, doping, insulation, withstanding breakdown, etc.) depend on the width/thickness of a semiconducting or insulation or conductive layer. So, a width/thickness of a semiconducting or insulation or conductive layer is a parameter that one must consider and decide upon and is something that can be optimized through routine experimentation and it has been held where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. (MPEP §2144.05 II/III).
Regarding claim 19, Saito793 and Chen059 disclose all the limitations of claim 1 as discussed above on which this claim depends.
Saito793 and Chen059 do not explicitly teach the light-emitting element includes a total thickness less than 110 μm. However, Saito793 and Chen059 teach thickness of various layers of the light-emitting element including substrate (see full disclosure of Saito793 and Chen059) and thus makes it obvious that these values are parameters that one must consider and decide upon for optimizing the device size (as claimed), performance, and cost through routine experimentation and optimization to obtain optimal or desired characteristics of the device.
Furthermore, it is well-known in the art that a width/thickness of a semiconducting or insulation or conductive layer depends on a process technology, overall size of the device, and is a result-effective variable as electrical properties (conductivity, current, resistance, doping, insulation, withstanding breakdown, etc.) depend on the width/thickness of a semiconducting or insulation or conductive layer. So, a width/thickness of a semiconducting or insulation or conductive layer is a parameter that one must consider and decide upon and is something that can be optimized through routine experimentation and it has been held where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. (MPEP §2144.05 II/III).
Regarding claim 20, Saito793 and Chen059 disclose all the limitations of claim 19 as discussed above on which this claim depends.
Saito793 and Chen059 do not explicitly teach wherein the total thickness is between 70 μm˜90 μm. However, Saito793 and Chen059 teach thickness of various layers of the light-emitting element including substrate (see full disclosure of Saito793 and Chen059) and thus makes it obvious that these values are parameters that one must consider and decide upon for optimizing the device size (as claimed), performance, and cost through routine experimentation and optimization to obtain optimal or desired characteristics of the device.
Furthermore, it is well-known in the art that a width/thickness of a semiconducting or insulation or conductive layer depends on a process technology, overall size of the device, and is a result-effective variable as electrical properties (conductivity, current, resistance, doping, insulation, withstanding breakdown, etc.) depend on the width/thickness of a semiconducting or insulation or conductive layer. So, a width/thickness of a semiconducting or insulation or conductive layer is a parameter that one must consider and decide upon and is something that can be optimized through routine experimentation and it has been held where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. (MPEP §2144.05 II/III).
Claim 10-12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Saito793 in view of Chen059, as applied to claim 1 above, and further in view of Araki et al. (US publication 2012/0319162 A1), hereinafter referred to as Araki162.
Regarding claim 10, Saito793 and Chen059 disclose all the limitations of claim 1 as discussed above on which this claim depends.
Saito793 also teaches further including a buffer layer (11, [0032-0033]) conformably formed on the upper surface of the substrate and the plurality of protrusions (fig. 1).
Chen059 also teaches further including a buffer layer (104, [0013]) conformably formed on the upper surface of the substrate and the plurality of protrusions (fig. 1a-1b).
Saito793 and Chen059 do not explicitly disclose a buffer layer including aluminum oxynitride.
Araki162 discloses a buffer layer (2, fig. 1) including aluminum oxynitride ([0061]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Saito793 and Chen059 with that of Araki162 so that a buffer layer including aluminum oxynitride because (a) it is a known alternative and would have been familiar to a person of ordinary skill in the art to yield predictable results, and (b) it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use, In re Leshin, 125 USPQ 416.
Regarding claim 11, Saito793, Chen059, and Araki162 disclose all the limitations of claim 10 as discussed above on which this claim depends.
Saito793 also teaches wherein a ratio of an aluminum content to a nitrogen content of the buffer layer is between 0.45˜0.9 ([0032-0033]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Saito793 and Chen059 with that of Araki162 so that wherein a ratio of an aluminum content to a nitrogen content of the buffer layer is between 0.45˜0.9 for filling in irregularities on the substrate and thereby further flattening the crystal surface ([0033] of Saito793). Furthermore, it has been held where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. (MPEP §2144.05 II/III).
Regarding claim 12, Saito793, Chen059, and Araki162 disclose all the limitations of claim 10 as discussed above on which this claim depends.
Saito793 also teaches wherein a difference between an aluminum content of the buffer layer on a sidewall of the plurality of protrusions and an aluminum content of the buffer layer on the upper surface of the substrate is less than 5% ([0032-0033], fig. 1, less than 5% encompasses 0%).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Saito793 and Chen059 with that of Araki162 so that wherein a difference between an aluminum content of the buffer layer on a sidewall of the plurality of protrusions and an aluminum content of the buffer layer on the upper surface of the substrate is less than 5% for filling in irregularities on the substrate and thereby further flattening the crystal surface ([0033] of Saito793). Furthermore, it has been held where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. (MPEP §2144.05 II/III).
Regarding claim 14, Saito793 teaches wherein the buffer layer includes a thickness between 15 nm and 25 nm ([0032]).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Saito793 and Chen059 in view of Araki162, as applied to claim 11 above, and further in view of Liu et al. (US publication 2022/0344538 A1), hereinafter referred to as Liu538.
Regarding claim 15, Saito793, Chen059, and Araki162 disclose all the limitations of claim 11 as discussed above on which this claim depends.
Saito793, Chen059, and Araki162 do not explicitly disclose wherein a thickness of the buffer layer on a sidewall of the plurality of protrusions is smaller than a thickness of the buffer layer on the upper surface of the substrate.
Liu538 discloses wherein a thickness of the buffer layer (200, [0024]) on a sidewall of the plurality of protrusions is smaller than a thickness of the buffer layer on the upper surface of the substrate (fig. 6).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Saito793, Chen059, and Araki162 with that of Liu538 so that wherein a thickness of the buffer layer on a sidewall of the plurality of protrusions is smaller than a thickness of the buffer layer on the upper surface of the substrate so that lattice defects that may form in the epitaxial layered structure can be greatly reduced ([0024]).
Allowable Subject Matter
Claims 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 13, the claim contains the following limitations: “wherein a difference between an aluminum content of the buffer layer on a sidewall of the plurality of protrusions and an aluminum content of the buffer layer on the upper surface of the substrate is greater than 5% but less than 12%” and none of the prior art of record discloses, teaches or fairly suggests, alone or in combinations when taken in combination with all other limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mohammed R Alam whose telephone number is 469-295-9205 and can normally be reached between 8:00am-6:00pm (M-F) or by e-mail via Mohammed.Alam1@uspto.gov.
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/MOHAMMED R ALAM/Primary Examiner, Art Unit 2897