Office Action Predictor
Last updated: April 15, 2026
Application No. 18/225,440

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CHANNEL STRUCTURES USING MULTIPLE BOTTOM-UP OXIDATION APPROACHES

Non-Final OA §103
Filed
Jul 24, 2023
Examiner
HARRISON, MONICA D
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
2y 1m
To Grant
98%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allow Rate
857 granted / 936 resolved
+23.6% vs TC avg
Moderate +7% lift
Without
With
+6.7%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
17 currently pending
Career history
953
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
37.5%
-2.5% vs TC avg
§102
44.2%
+4.2% vs TC avg
§112
5.4%
-34.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 936 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority This application, which discloses and claims only subject matter disclosed in prior Application No. 16/240,156, filed 1/4/19, appears to claim only subject matter directed to an invention that is independent and distinct from that claimed in the prior application, and names the inventor or at least one joint inventor named in the prior application. Accordingly, this application may constitute a divisional application. Should applicant desire to claim the benefit of the filing date of the prior application, attention is directed to 35 U.S.C. 120, 37 CFR 1.78, and MPEP § 211 et seq. The presentation of a benefit claim may result in an additional fee under 37 CFR 1.17(w)(1) or (2) being required, if the earliest filing date for which benefit is claimed under 35 U.S.C. 120, 121, 365(c), or 386(c) and 1.78(d) in the application is more than six years before the actual filing date of the application. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 12 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Radosavljevic et al (US 2013/0270512 A1) in view of Kuhn et al (9,595,581 B2). Regarding claim 12, Radosavljevic et al discloses an integrated circuit structure (Figure 3A, references 110 and 1120), comprising: a vertical arrangement of nanowires (Figure 3A, references 112A, 112B, 122A and 122B), a gate stack (Figure 3A, references 115, 140, 125 and 145) over the vertical arrangement of nanowires (Figure 3A, references 112A, 112B, 122A and 122B), around each of the nanowires (Figure 3A, references 112A, 112B, 122A and 122B), wherein the gate stack (Figure 3A, references 115, 140, 125 and 145) comprises a conductive gate electrode (paragraph 0033). However, Radosavljevic et al does not disclose wherein all nanowires of the vertical arrangement of nanowires are oxide nanowires. Kuhn et al discloses wherein all nanowires of the vertical arrangement of nanowires are oxide nanowires (column 10, lines 47-50). It would have been obvious, prior to the effective filing date of the instant application, for one having ordinary skill in the art, to modify Radosavljevic et al with the teachings of Kuhn et al for the purpose of forming all nanowires as oxide nanowires in order to avoid creating a very high-capacitance parasitic region between the subsequently formed gate and the source drain structure in microelectronic structures. Regarding claim 12, Radosavljevic et al discloses in view of Kuhn et al discloses wherein the oxide nanowires of the vertical arrangement of nanowires have an oxidation catalyst layer thereon (Kuhn et al column 5, lines 57-67 thru column 6, lines 1-3; a prima facie case of obviousness as stated above). Allowable Subject Matter Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art does not disclose nor fairly suggest an integrated circuit structure, further comprising: a gate contact above the vertical arrangement of nanowires, the gate contact in contact with a top surface of the conductive gate electrode; and an interconnect structure below the vertical arrangement of nanowires, wherein a conductive via of the interconnect structure is in contact with a bottom surface of the conductive gate electrode, wherein the conductive gate electrode acts as a conductive via between the gate contact and the interconnect structures (claim 13) further incorporated into independent claim 12 and in the context of its recited apparatus, along with its depending claims. Claims 1-11 and 15-20 are allowed over the prior art of record. The following is an examiner’s statement of reasons for allowance: The prior art does not disclose nor fairly suggest an integrated circuit structure and a computing device, comprising: the first vertical arrangement of nanowires having an active uppermost nanowire and an oxide bottommost nanowire, the second vertical arrangement of nanowires having an oxide uppermost nanowire and an active bottommost nanowire, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires and co-planar bottommost nanowires; a first gate structure over the first vertical arrangement of nanowires; and a second gate structure over the second vertical arrangement of nanowires and around the oxide bottommost nanowire as described in independent claims 1 and 15 and in the context of their recited apparatuses, along with their depending claims. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Smith et al (US 2019/0172828 A1) discloses an apparatus having stacked gates and method of manufacturing thereof. However, Smith et al does not disclose the allowable claimed subject matter as stated above. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MONICA D HARRISON whose telephone number is (571)272-1959. The examiner can normally be reached M-F 7-4:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MONICA D HARRISON/Primary Examiner, Art Unit 2815 mdh December 11, 2025
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Prosecution Timeline

Jul 24, 2023
Application Filed
Dec 11, 2025
Non-Final Rejection — §103
Apr 02, 2026
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
98%
With Interview (+6.7%)
2y 1m
Median Time to Grant
Low
PTA Risk
Based on 936 resolved cases by this examiner. Grant probability derived from career allow rate.

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