Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The action is in response to claims dated 7/1/2026.
Claims pending in the case: 1-20
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 8, 10-11, 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Clemons (US 20240231928) in view of Grigg (US 20150229622) and Xiong (US 20250117490).
Grigg and Xiong not used in the prior office action.
Regarding Claim 1, Clemons teaches, A system for dynamic allocation of computational resources for optimized performance of machine learning (ML) models, the system comprising: a processing device; a non-transitory storage device containing instructions when executed by the processing device (Clemons: [22]), causes the processing device to:
….
receive a request to execute a machine learning (ML) model from the user device, wherein the ML model comprises a neural network (Clemons: [20, 35]: scheduled task request to execute the task ML model; [30]: “the dynamic ML models 134 are previously trained dynamic deep neural networks (DNNs)”);
determine computational requirements associated with the ML model (Clemons: Fig. 2, [30]: resource manager determines resources for the ML models);
determine a subset of computational resources from a pool of computational resources to execute the ML model based on the computational requirements associated with the ML model (Clemons: [36]: determine resource based on task requirement);
allocate the subset of computational resources to the ML model (Clemons: [36]: “sending, to each dynamic ML model 134, an amount of computational resources allocated to a corresponding task” - allocate resource based on task requirement); and
execute the ML model using the subset of computational resources (Clemons: Fig. 2, [38]: execute task) and
determine an occurrence of a trigger event during the execution of the ML model (Clemons: Fig. 7, [37, 47, 54, 58]: performance trigger; [37]: "depending on execution time availability and the current accuracy" - trigger event of a change in performance or accuracy; [31]: "task priorities can include static priorities ..., as well as dynamic priorities that are computed based on how well the target and minimum performance requirements are being met"), …;
Clemons does not specifically teach,
execute an authentication to authenticate an identity of a user, wherein the authentication comprises a predefined motion with a user device;
wherein the occurrence of the trigger event comprises memory leaks associated with increased memory demand;
Grigg teaches, execute an authentication to authenticate an identity of a user, wherein the authentication comprises a predefined motion with a user device (Grigg: [35]: authentication may be a predefined motion with a user device);
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Clemons and Grigg because the combination would enable using an authentication step of a motion with a user device prior to accessing an application. One of ordinary skill in the art would have been motivated to combine the teachings because it is a common practice to have an authentication step to provide access to applications on a device. The combination helps to restrict unwanted access to information (see Grigg [1]);
Xiong further teaches, wherein the occurrence of the trigger event comprises memory leaks associated with increased memory demand (Xiong: [6, 53]: dynamic resource allocation based on identified vulnerabilities; [49]: vulnerability may be memory leaks);
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Clemons, Grigg and Xion because the combination would enable assessing resource allocation using not only a metric of performance loss but also identified vulnerabilities leading to it. One of ordinary skill in the art would have been motivated to combine the teachings because combination helps to address software vulnerabilities in software applications and avoid failures (see Xiong [3]);
Regarding claim 2, Clemons, Grigg and Xion teach the invention as claimed in claim 1 above and, wherein the computational requirements comprise at least processing power, memory, storage, network bandwidth, energy consumption, inference speed, numerical precision, and/or parallelism (Clemons: [64]: “computational resources, such as execution time, system memory, energy, or the like, on a computing system”; [19, 31]: performance requirement).
Regarding claim 8, Clemons, Grigg and Xion teach the invention as claimed in claim 1 above and, wherein executing the instructions further causes the processing device to:
capture information associated with the trigger event (Clemons: Fig. 7, [37, 47, 54, 58-59]: performance trigger; [37]: “depending on execution time availability and the current accuracy” – trigger event of a change in performance or accuracy; [31]: “task priorities can include static priorities …, as well as dynamic priorities that are computed based on how well the target and minimum performance requirements are being met”; compute performance) (Xiong: [30, 32]: analyze software vulnerabilities to determine fix);
determine an effect of the trigger event on the execution of the ML model; dynamically allocate additional computational resources to the ML model in response to determining the effect of the trigger event on the execution of the ML model (Clemons: [58-59]: adjust based on computed performance) (Xiong: [30, 32]: analyze software vulnerabilities to determine fix); and
execute the ML model using the subset of computational resources and the additional computational resources (Clemons: [58-59]: adjust based on computed performance) (Xiong: [30, 32]: analyze software vulnerabilities and adjust accordingly; [53]: dynamic resource allocation).
Regarding Claim(s) 10-11, this/these claim(s) is/are similar in scope as claim(s) 1-2 respectively. Therefore, this/these claim(s) is/are rejected under the same rationale.
Regarding Claim(s) 17, this/these claim(s) is/are similar in scope as claim(s) 8. Therefore, this/these claim(s) is/are rejected under the same rationale.
Regarding Claim(s) 18-19, this/these claim(s) is/are similar in scope as claim(s) 1-2 respectively. Therefore, this/these claim(s) is/are rejected under the same rationale.
Claim(s) 3-7, 9, 12-16, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Clemons (US 20240231928), Grigg (US 20150229622) and Xiong (US 20250117490) in view of Henry (US 20210286650).
Regarding claim 3, Clemons teaches the invention as claimed in claim 1 above and,
wherein the pool of computational resources comprises a plurality of processing units, wherein each processing unit comprises a plurality of cores (Clemons: [64]: computational resources). It would have been obvious that computation resources include processing units with cores;
Nonetheless, Henry teaches, resources comprise a plurality of processing units, wherein each processing unit comprises a plurality of cores (Henry: [3, 18]: processor with cores as resource for ML tasks).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Clemons, Grigg, Xiong and Henry because these are analogous arts and the combination would enable taking into account other common resources such as processor cores and storage types during resource allocation. One of ordinary skill in the art would have been motivated to combine the teachings because the combination would “better allocate computing resources for massive computing tasks” (see Henry [4-5]).
Regarding claim 4, Clemons. Grigg, Xiong and Henry teach the invention as claimed in claim 3 above and, wherein the plurality of processing units comprises at least central processing units (CPUs), graphics processing units (GPUs), tensor processing units (TPUs), field-programmable gate arrays (FPGAs), and/or application-specific integrated circuits (ASICs) (Henry: [2, 68]: CPU, GPU etc.).
Regarding claim 5, Clemons, Grigg, Xiong and Henry teach the invention as claimed in claim 4 above and,
wherein executing the instructions to determine the subset of computational resources further causes the processing device to:
determine a group of cores from the plurality of processing units; allocate the group of cores to the ML model; and execute the ML model using the group of cores (Henry: [3, 68]: allocate cores and execute ML tasks).
Regarding claim 6, Clemons, Grigg and Xion teach the invention as claimed in claim 1 above and, wherein the computational resources comprise one or more memory units, wherein the one or more memory units comprises at least a random access memory (RAM), a cache memory, a video RAM, a high bandwidth memory (HBM), a graphics double data rate (GDDR) memory, and/or a unified memory (Clemons: [64]: computational resources include storage)
Henry further teaches, types of memory units (Henry: [3, 59]:storage types of ROM, RAM etc.).
The same motivation to combine stated above applies.
Regarding claim 7, Clemons, Grigg, Xiong and Henry teach the invention as claimed in claim 6 above and, wherein executing the instructions to determine the subset of computational resources further causes the processing device to: determine a group of memory units; allocate the group of memory units to the ML model; and execute the ML model using the group of memory units (Clemons: [64]: “computational resources, such as execution time, system memory, energy, or the like, on a computing system”; [19, 31]: performance requirement) (Henry: [3, 59, 68]: allocate resources and execute ML tasks).
Regarding claim 9, Clemons, Grigg and Xion teach the invention as claimed in claim 8 and,
Henry further teaches, wherein the trigger event further comprises at least a change in dataset size, a change in model complexity, convergence issues, increase in concurrency, model ensembling, fault occurrences, and/or adversarial attacks (Henry: [31, 38, 42, 44, 49-50]: dynamic monitoring of sparsity (complexity/convergence), accuracy and other computation metric to adjust allocation of resources to neural network computing).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Clemons, Grigg, Xiong and Henry because these are analogous arts and the combination would enable taking into account events affecting resources to dynamically adjust resource allocation. One of ordinary skill in the art would have been motivated to combine the teachings because the combination would “better allocate computing resources for massive computing tasks” (see Henry [4-5]).
Regarding Claim(s) 12-16, this/these claim(s) is/are similar in scope as claim(s) 3-7 respectively. Therefore, this/these claim(s) is/are rejected under the same rationale.
Regarding Claim(s) 20, this/these claim(s) is/are similar in scope as claim(s) 3. Therefore, this/these claim(s) is/are rejected under the same rationale.
Response to Arguments
Applicants’ amendments have been fully considered and overcome the 35 U.S.C. § 101 rejection. These rejections are respectfully withdrawn.
Applicants’ prior art arguments have been fully considered but since they pertain to the amended sections of the claim, they are considered moot in view of the new grounds of rejection presented above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure in the attached 892.
Applicants’ amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MANDRITA BRAHMACHARI whose telephone number is (571)272-9735. The examiner can normally be reached Monday to Friday, 11 am to 8 pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tamara Kyle can be reached at 571 272 4241. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Mandrita Brahmachari/Primary Examiner, Art Unit 2144
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