DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/08/2026 has been entered.
Response to Amendment
Examiner acknowledges the amendments made to claims 1-5,8,9 and 11. New claims 12-14 have been added.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The previous rejection of claim 5 under 35 U.S.C. 112(a) is withdrawn in light of the amendments made to claim 5.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 4 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 4 limits that each pair of one of the first layers and one of the second layers has a thickness of 45nm. Independent claim 1 already limits the first layers to have a thickness of 15 nm and the second layers to have a thickness of 30nm, equating to a total pair thickness of 45 nm. Therefore, claim 4 does not further limit the subject matter of the claim upon which it depends.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3,6-8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida et al. (hereinafter Yoshida) (JP 2005072402 A) in view of Nibu et al. (hereinafter Nibu) (WO 2021187543 A1) and Hong et al. (hereinafter Hong) (US 20180240936 A1)
Examiner notes an attached machine translation will be used for the claim mapping of Yoshida for the remainder of the Office Action and the US 20230119356 A1 publication of Nibu will be used for the claim mapping of Nibu for the remainder of the instant application. See PTO-892 form.
Regarding claim 1, Yoshida discloses in Fig. 1,
A semiconductor laser device [Fig. 1] (Para. [0028]) comprising:
a first semiconductor layer [2A] (Para. 0028]); and
an active layer [4] (Para. [0027]) provided above the first semiconductor layer [2A] (Para. [0028]),
wherein the first semiconductor layer [2A] is a superlattice layer (Para. [0043]) and includes a plurality of first layers [2A1] and a plurality of second layers [2A2] (Para. [0043]),
wherein:
the plurality of first layers [2A1] and the plurality of second layers [2A2] are alternately stacked upon each other (Para. [0043]) (see Fig. 1C),
thicknesses of the plurality of first layers [2A1] are equal to each other (Paras. [0045,0046]), and thicknesses of the plurality of second layers [2A2] are equal to each other (Paras. [0044,0047,0048]),
the active layer [4] (Para. [0027]) and a central portion of the first semiconductor layer [2A] form a mesa [7] (Para. [0029]), and
the first semiconductor layer [2A] includes (i) a first portion included in the mesa [7] (Para. [0029]) and (ii) a second portion below the mesa [portion of 2A extending to edges of 1] (Para. [0028])
Yoshida fails to disclose,
the second portion including a larger number of pairs of the first layers and the second layers than the first portion such that the second portion is thicker than the first portion
each of the plurality of first layers has a thickness of 15nm, and each of the plurality of second layers has a thickness of 30 nm,
Nibu discloses in Fig. 1,
a second portion [133a] (Para. [0043]) of a superlattice layer [133] (Para. [0042]) with a larger number of pairs of first and second layers than a first portion [133b] (Paras. [0042,0043]) of a superlattice layer [133] (Para. [0042]) such that the second portion [133a] is thicker than the first portion [133b] (Para. [0043])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the thickness relationships of the superlattice layers in the mesa structure of Nibu with the superlattice structure of Yoshida for the purpose of accurately controlling position of the stacking surface of the superlattice structure and stabilizing output characteristics. (Nibu Para. [0079])
Yoshida in view of Nibu fails to disclose,
each of the plurality of first layers has a thickness of 15nm, and each of the plurality of second layers has a thickness of 30 nm,
Hong discloses in Fig. 2,
a superlattice structure [37] (Para. [0050]) including a plurality of first layers [18] (Para. [0050]) with a thickness [T5] of 15nm (Para. [0050]), and a plurality of second layers [17] (Para. [0050]) with a thickness [T4] of 30nm (Para. [0050]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the superlattice layer thicknesses of Hong in the modified device of Yoshida for the purpose of controlling defects in the superlattice layer. (Hong Para. [0050])
Regarding claim 2, Yoshida in view of Nibu and Hong as applied to claim 1 above further discloses in Yoshida Fig. 1,
wherein the plurality of first layers [2A1] comprise InP (Para. [0043]), and
wherein the plurality of second layers [2A2] comprise InGaAsP (Para. [0043]) or AlInGaAs.
Examiner notes the interpretation of the optional limitation of claim 2 for purposes of examination in the instant application is understood to be “the second layers are formed of InGaAsP”
Regarding claim 3, Yoshida in view of Nibu and Hong as applied to claim 1 above further discloses in Yoshida Fig. 1,
a second semiconductor layer [2B] (Para. [0028]) provided above the active layer [4] (Paras. [0028,0029]),
wherein an effective refractive index of the first semiconductor layer [2A] is larger than a refractive index of the second semiconductor layer [2B] (Para. [0048]).
Regarding claim 4, Yoshida in view of Nibu and Hong as applied to claim 1 above further discloses in Hong Fig. 2,
wherein each pair of one of the first layers [18] and one of the second layers [17] has a thickness of 45nm (Para. [0050])
With a thickness value [T4] of 30nm and a thickness value [T5] of 15nm, the thickness of the pair of first and second layers is 45nm. (Hong Para. [0050])
Regarding claim 6, Yoshida in view of Nibu and Hong as applied to claim 1 above further discloses in Yoshida Fig. 1,
wherein the second portion [portion of 2A extending to edges of 1] of the first semiconductor layer [2A] extends beyond the mesa [7] in a lateral direction (Para. [0029]) (see Fig. 1B).
Regarding claim 7, Yoshida in view of Nibu and Hong as applied to claim 3 above further discloses in Yoshida Fig. 1,
wherein the first semiconductor layer [2A] is an n-type semiconductor layer (Para. [0028]), and
Regarding claim 8, Yoshida in view of Nibu and Hong as applied to claim 3 above further discloses in Yoshida Fig. 1,
wherein the second semiconductor layer [2B] is a p-type semiconductor layer (Para. [0032]) and,
the semiconductor device further comprises buried layers [8,9] (Para. [0029]) provided on both sides of the mesa [7] (Paras. [0029,0033]) (see Fig. 1B).
Regarding claim 10, Yoshida in view of Nibu and Hong as applied to claim 1 above further discloses in Nibu Fig. 1,
wherein the second portion [133a] of the first semiconductor layer [133] includes at least twice as many pairs of the first layers and the second layers as the first portion [133b]of the first semiconductor layer [133] (Para. [0043])
Claims 5 and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida in view of Nibu and Hong as applied to claim 1 above, and further in view of Ooshika (US 20130181188 A1).
Regarding claim 5, Yoshida in view of Nibu and Hong discloses the device outlined in the rejection of claim 1 above but fails to disclose,
Wherein the second portion of the first semiconductor layer includes 20 pairs of the first layers and the second layers and has a thickness of 900nm.
Ooshika discloses in Fig. 1,
a first portion of a superlattice structure [16] (Para. [0057]) including 10 pairs of first [16A] (Para. [0057]) and second layers [16B] (Para. [0057]) and a second portion of a superlattice structure [18] (Para. [0058]) including 20 pairs of first [18A] (Para. [0058])and second layers [18B] (Para. [0058])
It would have been obvious to implement the number of sets of superlattice layers as shown in Ooshika with the first and second layers of the first and second portions of the modified device of Yoshida for the purpose of achieving a strain buffer effect. (Ooshika Para. [0058])
With 20 pairs of layers with a total pair thickness of 45nm, the complete thickness is 20 pairs * 45nm which equates to 900nm.
Regarding claim 11, Yoshida in view of Nibu, Hong and Ooshika as applied to claim 5 above further discloses,
wherein the first portion of the first semiconductor layer includes 10 pairs of the first layers and the second layers (Ooshika Para. [0057]), and
wherein the second portion of the first semiconductor layer includes 20 pairs of the first layers and the second layers (Ooshika Para. [0058])
Regarding claim 12, Yoshida in view of Nibu, Hong and Ooshika as applied to claim 11 above further discloses,
wherein the first portion of the first semiconductor layer has a thickness of 450 nm [Hong Fig. 2[ (Hong Para. [0050]) and (Ooshika Para. [0058]), and
wherein the second portion of the first semiconductor layer has a thickness of 900 nm (Hong Para. [0050]) (Ooshika Para. [0058]).
With 10 pairs of layers with a total pair thickness of 45nm, the complete thickness is 10 pairs * 45nm which equates to 450nm and,
With 20 pairs of layers with a total pair thickness of 45nm, the complete thickness is 20 pairs * 45nm which equates to 900nm. (see Hong Para. [0050] and Ooshika Paras. [0057,0058])
Regarding claim 13, Yoshida in view of Nibu, Hong and Ooshika as applied to claim 5 above further discloses,
wherein the second portion of the first semiconductor layer includes 20 pirs of the first layers and the second layers (Ooshika Para. [0058])
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshida in view of Nibu, Hong, Kneissl et al. (hereinafter Kneissl) (US 6597717 B1) and further in view of Kano (WO 2019188318 A2).
Examiner notes an attached machine translation will be used for the claim mapping of Kano. See PTO-892 form.
Regarding claim 9, Yoshida discloses in Fig. 1,
A method of manufacturing a semiconductor laser device [10] (Para. [0028]), the method comprising:
providing a first semiconductor layer [2A] (Para. [0028]) as a superlattice layer (Para. [0043])including a plurality of first layers [2A1] (Para. [0043]) and a plurality of second layers [2A2] (Para. [0043]), the plurality of first
wherein the first semiconductor layer [2A] is a superlattice layer (Para. [0043]) and includes a plurality of first layers [2A1] (Para. [0043]) and a plurality of second layers [2A2] (Para. [0043]),
the plurality of first layers [2A1] and the plurality of second layers [2A2] being alternately stacked upon each other (Para. [0043]),
thicknesses of the plurality of first layers [2A1] being equal to each other (Paras. [0045,0046]), and thicknesses of the plurality of second layers [2A2] being equal to each other (Paras. [0044,0047,0048]),
providing an active layer [4] (Para. [0028]) above the first semiconductor layer [2A] (Para. [0028])
forming the active layer [4] (Para. [0027]) and a central portion of the first semiconductor layer [2A] form a mesa [7] (Para. [0029])
wherein the first semiconductor layer [2A] includes (i) a first portion included in the mesa [7] (Para. [0029]) and (ii) a second portion below the mesa [portion of 2A extending to edges of 1] (Para. [0028])
Yoshida fails to disclose,
each of the plurality of the first layers having a thickness of 15 nm, and each of the plurality of second layers having a thickness of 30 nm;
measuring a thickness of the first semiconductor layer by X-ray diffraction; and
providing an active layer above the first semiconductor layer after the measuring of the thickness is performed and,
the second portion including a larger number of pairs of the first layers and the second layers than the first portion such that the second portion is thicker than the first portion.
Nibu discloses in Fig. 1,
a second portion [133a] (Para. [0043]) of a superlattice layer [133] (Para. [0042]) with a larger number of pairs of first and second layers than a first portion [133b] (Paras. [0042,0043]) of a superlattice layer [133] (Para. [0042]) such that the second portion [133a] is thicker than the first portion [133b] (Para. [0043])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the thickness relationships of the superlattice layers in the mesa structure of Nibu with the superlattice structure of Yoshida for the purpose of accurately controlling position of the stacking surface of the superlattice structure and stabilizing output characteristics. (Nibu Para. [0079])
Yoshida in view of Nibu fails to disclose,
each of the plurality of the first layers having a thickness of 15 nm, and each of the plurality of second layers having a thickness of 30 nm;
measuring a thickness of the first semiconductor layer by X-ray diffraction; and
providing an active layer above the first semiconductor layer after the measuring of the thickness is performed
Hong discloses in Fig. 2,
a superlattice structure [37] (Para. [0050]) including a plurality of first layers [18] (Para. [0050]) with a thickness [T5] of 15nm (Para. [0050]), and a plurality of second layers [18] (Para. [0050]) with a thickness [T4] of 30nm (Para. [0050]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the superlattice layer thicknesses of Hong in the modified device of Yoshida for the purpose of controlling defects in the superlattice layer. (Hong Para. [0050])
Kneissl discloses,
measuring a thickness of a superlattice structure [175 Fig. 4b] by X-ray diffraction (Col. 5, lines 3-5)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the X-ray diffraction method of measuring a thickness of a superlattice layer as shown in Kneissl with the superlattice of Yoshida for the purpose of non-destructive and accurate thickness measurements. (Kneissl Col. 5, lines 3-5)
Yoshida in view of Nibu, Hong and Kneissl fails to disclose,
providing an active layer above the first semiconductor layer after the measuring of the thickness is performed
Kano discloses,
measuring a thickness of a stacked structure [104] by X-ray diffraction [Step S12 Fig. 7] (Paras. [60,61]) before subsequent growth steps [S15 Fig. 7] (Para. [62]) by measuring a period of a stacked structure and determining a thickness of the layer based on the measured period and number of pairs (Paras. [54-56])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the X-ray diffraction thickness measurement of the superlattice layer of the modified method of Yoshida before subsequent growth steps for the purpose of avoid full manufacturing of devices out of a desired standard and specification. (Kano Para. [65])
Regarding claim 14, the modified method of Yoshida discloses the method outlined in the rejection of claim 9 above and further discloses,
Wherein the measuring of the thickness of the first semiconductor layer by X-ray diffraction (Kneissl Col. 5, lines 3-5) includes measuring a period of 45 nm (Hong Para. [0050]) of the superlattice layer and determining the thickness of the first semiconductor layer based on the measured period of 45 nm (Hong Para. [0050]) and a number of pairs of the first layers and the second layers included in the first semiconductor layer (Kano Paras. [54-56]).
Kano discloses the measurement specific periods of a stacked structure and a sum of the pair thicknesses to arrive at a sum of the layer thickness. Hong discloses the period thickness value of 45nm as limited.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNTER J NELSON whose telephone number is (571)270-5318. The examiner can normally be reached Mon-Fri. 8:30am-5:00 ET.
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/H.J.N./Examiner, Art Unit 2828 /TOD T VAN ROY/Primary Examiner, Art Unit 2828
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