DETAILED ACTION
This Office Actions is in response to communication filed on 07/25/2023. Claims 1-20 are pending. Claim 1 and 11 are in independent form.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the terms “relatively higher power state” and “relatively lower power state” are relative terms which renders the claim indefinite. The terms “relatively higher power state” and “relatively lower power state” are not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. It is unclear how, or which value, to indicate the “power state” to be considered as “relatively higher” or “relatively lower”. The examiner suggests to amend the claims to further defined the “relatively higher” and the “relatively lower”, or to remove the undefined terms.
Regarding claim 11, it is an information handling system claim having similar limitations cited in claim 1, so it is also rejected under the same rational.
Regarding claims 2-9 and 12-19 are also rejected due to the dependency on the rejection of claim 1 and 11.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 10-12, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over SEKIZAWA et al. US Pub. No. US 20210141667 A1 (hereafter SEKIZAWA), in further view of Sultenfuss et al. US Pub. No. US 20150067362 A1 (hereafter Sultenfuss).
Regarding claim 1, SEKIZAWA teaches the invention substantially as claimed: A method, comprising using at least one programmable integrated circuit of an information handling system to: execute a process that implements multiple different process tasks, each of the multiple different process tasks being initially scheduled for performance at a designated target trigger time; (e.g. FIG. 2-4, and [0086]: “In view of the above, the information processing apparatus 1 according to the present embodiment generates one or more job groups by grouping multiple jobs of execution targets in descending order of the priority. The information processing apparatus 1 schedules the execution timings regarding the multiple jobs such that scheduling of respective jobs included in the job group including the job having the higher priority (hereinafter, also referred to as a specific job group) is implemented by priority over scheduling of respective jobs included in the other job groups. In this case, the information processing apparatus 1 schedules the execution timings regarding the respective jobs included in the specific job group such that an execution completion time of all the jobs included in the specific job group satisfies a predetermined condition.”) the citation discloses a job group/a process, that comprises multiple jobs/multiple different process tasks, and the multiple jobs is scheduled the execution timing.
reschedule one or more of the target trigger times of the multiple different process tasks to respective actual performance times such that the actual performance times of each of the multiple different process tasks simultaneously occur together with the actual performance times of other of the multiple different process tasks at a common synchronized performance time; (e.g. FIG. 2-4, and [0204]: “In the processing in S52, the information processing apparatus 1 may also be configured to specify combinations of jobs that may be executed at the same time in the job execution apparatus 3 among the respective jobs included in the job group specified in the processing in S51, and further specify a combination in which the number of nodes used for executing the jobs included in the respective combinations is the highest (hereinafter, also referred to as a specific combination) among the specified combinations of the jobs. The information processing apparatus 1 may also be configured to specify the schedule in which the respective jobs included in the specified specific combination are executed at the same time as a schedule corresponding to the job group specified in the processing in S51.”) the citation discloses the concept of scheduling/rescheduling, the jobs to execute at the same time. FIG. 3 discloses the reschedule of “job 5” to start at the same time with “job 1” and “job 2”.
and execute the process to simultaneously perform the multiple different process tasks together at the common synchronized performance time; (e.g. [0050]: “The information processing system 10 also includes a job execution apparatus 3 that executes the jobs in accordance with the scheduling performed by the information processing apparatus 1.” and [0204]: “In the processing in S52, the information processing apparatus 1 may also be configured to specify combinations of jobs that may be executed at the same time in the job execution apparatus 3 among the respective jobs included in the job group specified in the processing in S51”) The citation discloses the job execution apparatus that responsible for executing the jobs accordance with the performed scheduling.
SEKIZAWA fails to teach where the method further comprises operating one or more power-consuming hardware components of the information handling system in a first relatively higher power state when performing any one or more of the multiple different process tasks, and operating the one or more power-consuming hardware components of the information handling system in a second relatively lower power state when not performing any of the multiple different process tasks.
However, Sultenfuss teaches where the method further comprises operating one or more power-consuming hardware components of the information handling system in a first relatively higher power state when performing any one or more of the multiple different process tasks, (e.g. [0037]: “For example, a load 503 including a CPU can consume relatively higher power when operating in a high performance mode and can consume relatively lower power when operating in a low performance mode. Loads 503 can change modes of operation rapidly. For example, a load 503 including a CPU can operate in a low power mode consuming relatively low power, switch to a high performance mode consuming higher power to process a packet received on a communication network, and switch back to a low performance mode after processing the packet.”) the citation discloses a CPU/hardware, consume relatively higher power when operates in a high performance mode/first relatively high power, when it needs to process a packet/perform a process tasks.
and operating the one or more power-consuming hardware components of the information handling system in a second relatively lower power state when not performing any of the multiple different process tasks. (e.g. [0037]: “For example, a load 503 including a CPU can consume relatively higher power when operating in a high performance mode and can consume relatively lower power when operating in a low performance mode. Loads 503 can change modes of operation rapidly. For example, a load 503 including a CPU can operate in a low power mode consuming relatively low power, switch to a high performance mode consuming higher power to process a packet received on a communication network, and switch back to a low performance mode after processing the packet.”) the citation discloses a CPU/hardware, consume relatively lower power when operating in a low performance mode/second relatively low power, after processing the packet. Because the CPU finished processing the packet and switch back to low performance mode, it would imply that no other packet available.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the where the method further comprises operating one or more power-consuming hardware components of the information handling system in a first relatively higher power state when performing any one or more of the multiple different process tasks, and operating the one or more power-consuming hardware components of the information handling system in a second relatively lower power state when not performing any of the multiple different process tasks, as taught in Sultenfuss’s invention into SEKIZAWA’s invention because the addition features would help to improve the overall efficiency of the system and lowering the energy consumption by matching power usage to the actual processing activities, and also improve overall system power management without affecting the coordinated execution of the multiple processing tasks.
Regarding claim 2, SEKIZAWA, in view of Sultenfuss, discloses the method of claim 1, and SEKIZAWA further teaches further comprising using the at least one programmable integrated circuit to: define sequential blocks of time as sequential schedule blocks that are available for scheduling of process tasks; (e.g. FIG. 2-3) the citation discloses the block of time from 0-20 is available to reschedule Job-5
define each of the target trigger times for each given process task as respective target schedule blocks for the given process task; (e.g. FIG. 2-3) the citation discloses each job has it own block of time for execution.
and define the common synchronized performance time as a synchronized schedule block for performing the multiple different process tasks together at the common synchronized performance time. (e.g. FIG. 2-3) the citation discloses the time 0 that jobs 2 and 3 could execute together, and at the time 50, jobs 1 and 5 could execute together.
Regarding claim 10, SEKIZAWA, in view of Sultenfuss, discloses the method of claim 1, and Sultenfuss further teaches where the information handling system is a battery powered information handling system; (e.g. [0022]: “In a particular embodiment, an information handling system uses battery packs to provide power. Battery power can be the sole power source for a system, or it can augment other power sources.”)
and where the operating the one or more power-consuming hardware components of the information handling system in the first relatively higher power state comprises operating the one or more power-consuming hardware components of the information handling system on battery power in the first relatively higher power state; (e.g. [0026]: “For example, a high performance mode of operation of an information handling system can require that a battery pack provide a relatively high level of power. As the output voltage of the battery pack declines, the battery pack provides an increasing current in order to maintain the power level required to operate the information handling system in the high performance mode.”) The citation discloses the battery provide high power when the system operates in a high performance mode.
and where the operating the one or more power-consuming hardware components of the information handling system in the second relatively lower power state comprises operating the one or more power-consuming hardware components of the information handling system on battery power in the second relatively lower power state. (e.g. [0027]: “In an embodiment, reduced peak power provided by a battery pack prevents an information handling system from operating in a high performance mode, and the information handling system operates in a lower performance mode consuming less power.” and [0038]: “For example, power control module 501 can instruct an adaptive battery pack 502 to provide a lower voltage to a load 503 that is a CPU when the CPU is in a sleep state. In the sleep state, the CPU can consume less power at a lower voltage than in an operating state.”) The citation discloses the battery provide lower power when the CPU operates in a sleep state.
Regarding claim 11, it is an information handling system claim having similar limitations cited in claim 1, so it is also rejected under the same rational.
Regarding claim 12, it is an information handling system claim having similar limitations cited in claim 2, so it is also rejected under the same rational.
Regarding claim 20, it is an information handling system claim having similar limitations cited in claim 10, so it is also rejected under the same rational.
Claims 9, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over SEKIZAWA, and Sultenfuss, in further view of EUN US Pub. No. US 20210349762 A1.
Regarding claim 9, SEKIZAWA, in view of Sultenfuss, discloses the method of claim 1, and Sultenfuss further teaches where the at least one programmable integrated circuit controls a power state of the one or more power-consuming hardware components; (e.g. [0037]: “Loads 503 can operate in a plurality of modes, with each mode having a different power requirement. For example, a load 503 including a CPU can consume relatively higher power when operating in a high performance mode and can consume relatively lower power when operating in a low performance mode. Loads 503 can change modes of operation rapidly. For example, a load 503 including a CPU can operate in a low power mode consuming relatively low power, switch to a high performance mode consuming higher power to process a packet received on a communication network, and switch back to a low performance mode after processing the packet.”) the citation discloses the load 503 that comprises multiple modes for the CPU and can change the mode for the CPU as needed.
However, EUN teaches and where the first relatively higher power state is a modern standby state; (e.g. [0121]: “The power consumption in the “standby mode (standby state)” is the highest and power consumption in the SIR mode is the lowest.”) The citation discloses the concept of power consumption in the standby state is the highest.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the cause the where the first relatively higher power state is a modern standby state, as taught in EUN’s invention into SEKIZAWA, and Sultenfuss’s invention because the newly added limitation would enable the system to quickly perform the synchronized process tasks while remaining in a low power operating mode that is still ready to quickly resume activities, which improving power efficiency, reducing wake-up overhead, and maintain faster responsiveness while completing multiple tasks together.
Regarding claim 19, it is an information handling system claim having similar limitations cited in claim 9, so it is also rejected under the same rational.
Allowable Subject Matter
Claims 3-8, and 13-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20230048833 A1: a method for scheduling tasks, including: acquiring task information of a current task to be executed, the task information describing the current task to be executed; determining an execution time for the current task to be executed according to the task information; and comparing the execution time with a preset scheduling time corresponding to the current task to be executed, and adjusting an actual scheduling time corresponding to a next task to be executed according to the comparison result so as to determine whether to schedule the next task to be executed.
US 20210374652 A1: A job scheduling method comprising: identifying a first power consumption needed to execute a plurality of first jobs executed in a past and a plurality of nodes used to execute the plurality of first jobs; identifying a second power consumption needed for each of the plurality of nodes used to execute the plurality of first jobs to execute a job, based on the first power consumption and the plurality of nodes; identifying a first node of which the second power consumption is greater than a predetermined threshold value, from among the plurality of nodes.
US 20200104170 A1: a method for scheduling tasks comprises: retrieving a first task descriptor from a local memory, the task descriptor corresponding to a task scheduled for execution at the current time and comprising at least a task execution time, a frequency for performing the task, and a task identifier; determining whether the task descriptor is assigned to the processing group associated with the task scheduler for execution; if it is determined that the task descriptor is assigned to the processing group associated with the task scheduler for execution: determining whether the task descriptor is assigned to the task scheduler for execution; if it is determined that the task descriptor is assigned to task scheduler for execution: executing the task: updating the task execution time based on the current task execution time and the frequency for performing the task; and re-queuing the task descriptor in the local memory.
US 20140137122 A1: A method is disclosed for reducing peak power usage in a large computer system with multiple nodes by identifying jobs which can be scheduled to run at reduced frequency in order to reduce total power usage during certain time periods; The scheduler of the computer system's operating system performs steps providing for selected jobs on selected nodes of the computer system to be run at reduced frequency such that those jobs are partially processed during previously underutilized holes in the computer system schedule in order to reduce overall peak power during a period of processing.
Examiner has cited particular columns/paragraphs/sections and line numbers in the references applied and not relied upon to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
When responding to the Office action, applicant is advised to clearly point out the patentable novelty the claims present in view of the state of the art disclosed by the reference(s) cited or the objections made. A showing of how the amendments avoid such references or objections must also be present. See 37 C.F.R. 1.111(c).
When responding to this Office action, applicant is advised to provide the line and page numbers in the application and/or reference(s) cited to assist in locating the appropriate paragraphs
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN M NGUYEN whose telephone number is (703)756-1599. The examiner can normally be reached Monday-Friday: 9:30am - 5:30PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Pierre Vital can be reached at (571) 272-4215. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TUAN M NGUYEN/Examiner, Art Unit 2198
/PIERRE VITAL/Supervisory Patent Examiner, Art Unit 2198
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