Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 18/226,534 filed on 09/11/2023.
Election/Restrictions
Applicant’s election of Species A, claims 1-7, and 9-18 in the reply filed on 12/17/1025 is acknowledged. Accordingly, claims 8 and 19-20 are withdrawn.
Information Disclosure Statement
The references listed in the Information Disclosure Statement (IDS) filed on 08/07/2023 have been considered by the examiner (see attached PTO-1449 or PTO/SB/08A and 08B forms).
Drawings
The Drawings filed on 07/26/2023 have been considered.
Claim Objections
Claim 11 is objected to because of the following informalities: in the phrase, “ wherein the first semiconductor chip has an area, greater than an area of the second semiconductor chip”, the comma breaks the connection between “an area” and “greater than an area of the second semiconductor chip”, and the examiner does not believe that it was Applicant’s intent to do so. Removal of the comma is one obviously remedy.. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7, and 9-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The limitation, “a vertical connection conductor around the first semiconductor chip and the second semiconductor chip on the first redistribution structure”, as recited in claim 1, is consistent with the drawings (e.g., Fig. 7 or 8), but is sufficiently broad as to make the entire claim substantially broader than what the drawing and the remainder of the specification can support. In particular. the drawings appear \an arrangement of the frame or pillars to form a cage around the first and second semiconductor chips. Merely reciting that the “vertical connection conductor” is around” the two semiconductor chips does not make this clear. Part of the reason for this is that the use of the phrase “vertical connection conductor” instead of the phrase directly tied to the drawings (a set of “pillars” or a frame) leaves open the possibility that the Applicant wishes to claim other interpretations of the phrase, “vertical connection conductor” that are not explicitly shown in the drawings. Since the claim directed to any conductor whatsoever that may in some sense be “vertical”, and may carry out some form of “connection”, and maybe a conductor would exclude much of the prior art already well established, so long as it was found in the neighborhood of a pair of the semiconductor chip stacked one above the other, the examiner is obliged to respectfully inquire as to Applicant’s intended meaning for this limitation.
The limitation, “wherein the first logic chip comprises a first processor core portion and a logic portion, and the second logic chip comprises a second processor core portion and a memory interface portion”, as recited in claim 3, is unclear with several respects. First, it is unclear whether the phrase, “processor core portion”, appearing with regard to two separate elements of the claim, is intended to mean a literal portion of a processor core, or if it is intended to convey that the entire processor core itself a portion of greater whole. Of course it is possible that Applicant’s answer to this question would be different for each of the two instances of the phrase. Finally, since a processor core is understood by many in the field to be synonymous with a ‘central processing unit, it is unclear how the limitation taken as a whole further limits the notion of either a first to a second processor core, since the broadest reasonable understanding of a processor core would include both a “logic portion” and a memory interface portion”.
The limitation, “wherein the first logic chip comprises a first processor core portion and a logic portion”, and, “wherein the second logic chip comprises a second processor core portion and a memory interface portion “as recited in each of claims 16 and 19, are unclear in several respects. First, it is unclear whether the phrase “processor core portion”, appearing in each of these limitations, is intended to mean a literal portion of a processor core, or if it is intended to convey that the entire processor core itself a portion of a greater whole. Of course it is possible that Applicant’s answer to this question would be different for each of the two limitations. Finally, since a processor core is understood by many in the field to be synonymous with a central processing unit’, it is unclear how the limitation taken as a whole further limit the notion of either a first or a second processor core, since the broadest reasonable understanding or a processor core would include both a “logic portion” and a “memory interface portion”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, and 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over ZHAI et al. (US 20170141088 A1) in view of KIM et al. (US 8890329 B2).
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Regarding claim 1, ZHAI teaches in Fig. 7, “A semiconductor package, comprising:
a first redistribution structure (130lower) comprising a first redistribution layer;
a first semiconductor chip (142upper) on the first redistribution structure, the first
semiconductor chip comprising first lower pads (144) (see Fig. 5B), wherein the first lower pads are electrically connected to the first redistribution layer (130lower);
a second semiconductor chip (142upper) on the first semiconductor chip, the
second semiconductor chip comprising second upper pads (144),
a vertical connection conductor (140) around the first semiconductor chip and the
second semiconductor chip on the first redistribution structure, wherein the vertical connection conductor is electrically connected to the first redistribution layer (130);
a molded portion (152) on the first redistribution structure (130), wherein the molded portion surrounds the first semiconductor chip and the second semiconductor chip;
a second redistribution structure (160) on the second semiconductor chip
(142upper) and the vertical connection conductor (140), the second redistribution
structure comprising a second redistribution layer connected to the second upper pads and to the vertical connection conductor; and
a third semiconductor chip (172) (see Fig. 9A) on the second redistribution structure (160), the third semiconductor chip (172) comprising contact pads (174) electrically connected to the second redistribution layer (160) (via a third RDL (190) and the vertical connection conductor (170).
ZHAI does not explicitly teach including “first upper pads, and first through-electrodes electrically connecting the first lower pads to the first upper pads” of the first semiconductor chip (142upper) and first through-electrodes electrically connecting the first lower pads to the first upper pads; second lower pads of the second semiconductor chip, and second through-electrodes electrically connecting the second lower pads to the second upper pads, wherein the second lower pads are electrically connected to the first upper pads.
KIM teaches in Fig. 2 (and related texts or see the interpretation labels shown below) a first distribution layer (130); a first semiconductor chip (210) comprising first low pads, first upper pads, and first through-electrodes (211) electrically connecting the first upper pads to the first lower pads connected to the first distribution layer (130); and a second distribution layer (140); a second semiconductor chip (110) comprising second lower pads, second upper pads, and second through-electrodes (112) electrically connected to the first upper pads of the first semiconductor chip (210).
It would have been obvious to one having ordinary skill in the pertinent art before the effective filing date to employ the first and second chips with through electrodes as taught by KIM, since electronic products today require to have small sizes and high performance, and without effecting input/output terminals. The motivation is to reduce signal propagation time.
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Regarding claim 5, the limitation, “wherein the first semiconductor chip is electrically connected to the first redistribution layer by first conductive bumps”, is met by “144”, “146”, and “136” in combination, in Figs. 5A-5C (please see (please see ZHAI’s para. [0041]).
Regarding claim 6, the limitation, “a first non-conductive film surrounding the first conductive bumps between the first semiconductor chip and the first redistribution structure” is met by “an underfill material (150).
To further clarify that “the underfill is a composite material usually made of an
epoxy polymer which is considered as a non-conductive film that fills gaps between a chip and its carrier.
Regarding claim 7, the limitation, “wherein the vertical connection conductor comprises a plurality of conductive posts on the first redistribution structure, wherein the plurality of conductive posts are connected to the first redistribution layer, and wherein the molded portion surrounds the plurality of conductive posts.” Is met by conductive pillars 140 which serves as conductive posts (see para. [0140]).
This Application was searched in, https://iq.ip.com/discover in view of the limitations of the claimed invention. the search was ineffective.
Telephone Inquiry Contacts
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASMINE J CLARK whose telephone number is (571)272-1726. The examiner can normally be reached 8:30-5.30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ZANDRA SMITH can be reached at (571) 272 2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASMINE J CLARK/Primary Examiner, Art Unit 2899