DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on December 11th, 2025 is acknowledged.
Claims 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on December 11th, 2025.
Claim Objections
Claim 11 is objected to because of the following informalities: "third surface of the is" is grammatically incorrect. Appropriate correction is required.
Claims 12-16 are dependent on the objected claim and thus objected.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen (US 20060220259 A1).
Regarding claim 1, FIG. 44 and FIG. 49 of Chen teach a semiconductor package (paragraph 0017) comprising:
a first structure (610; FIG. 44; paragraph 0085);
a second structure (710; FIG. 44; paragraph 0085);
a plurality of first connection members including SnBi (620; FIG. 44; paragraph 0086); and
a plurality of second connection members including SAC (Sn, Ag and Cu) (760; FIG. 44; paragraph 0091),
wherein each first connection member of the plurality of first connection members has a first surface (620; FIG. 44; paragraph 0086) and a second surface (620; FIG. 44; paragraph 0086) opposite each other, and the first surface of each first connection member of the plurality of first connection members is bonded to the first structure,
a third surface (760; FIG. 44; paragraph 0091) of each second connection member of a plurality of second connection members is bonded to a corresponding second surface of a respective first connection member, and for each second connection member, a fourth surface (760; FIG. 44; paragraph 0091) of the second connection member that is opposite the third surface of the second connection member is bonded to the second structure,
the third surface of each second connection member is flat, and
a diameter of each second connection member (760; FIG. 49; paragraph 0097) decreases in a direction receding from the third surface of each second connection member.
Regarding claim 3, FIG. 44 of Chen teaches the semiconductor package of claim 1, further comprising an under-bump structure (770; FIG. 44; paragraph 0091) between the second connection member (760; FIG. 44; paragraph 0091) and the second structure (710; FIG. 44; paragraph 0085).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al..
Claim 2 would be allowable as Chen et al. teaches the semiconductor package of claim 1. Chen et al. does not teach an angle between a bottom surface of the second structure and a side surface of the second connection member being 60o to 80o as the angle cannot be exactly measured (FIG. 46).
However, the ordinary artisan would have recognized the 60o to 80o angle measurement to be a result effective variable affecting how the second connection members (760; FIG. 46: paragraph 0091) fit into the bump pads (753; FIG. 46: paragraph 0091) on the second structure (710; FIG. 46; paragraph 0085). Thus, it would have been obvious to set the angle within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B.
Claim 10 would be allowable as Chen et al. teaches the semiconductor package of claim 1. Chen et al. does not explicitly display a volume ratio of the first connection member to the second connection member being 0.4:1 to 0.5:1.
However, the ordinary artisan would have recognized the volumes of the connection members to be a result effective variable affecting the connection method (paragraph 0093). Thus, it would have been obvious to set the volume ratio within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B.
Claims 4, 5, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. in view of Terishima et al. (US 20120223430 A1).
Regarding claim 4, Chen et al. teaches the semiconductor package of claim 1. Chen et al. does not teach the package further comprising an oxide layer on a side surface of the second connection member.
Terishima teaches an oxide layer (paragraph 0019) formed on a Sn-Ag-Cu solder ball surface (paragraph 0010).
Chen et al and Terishima et al. are both analogous to the claimed invention in that they involve semiconductor packages with connection members. Therefore, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen et al. so that the package further comprises an oxide layer on a side surface of the second connection member. This is because the growing oxide layer on the solder ball is a natural phenomenon
Regarding claim 5. Chen et al. teaches the semiconductor package of claim 4. Chen et al. does not teach the oxide layer including at least one of: Sn oxide, Ag oxide and Cu oxide.
Terishima teaches forming a non-crystalline tin-oxide layer over the solder ball surface.
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen et al. so that the oxide layer includes at least an Sn oxide. This is because keeps the oxide layer from growing uncontrollably.
Regarding claim 6, the combination of Chen et al. in view of Terishima et al. teaches the semiconductor package of claim 4. Neither Chen et al. nor Terishima et al. teach the oxide layer having a height greater than 30% of a sum of heights of the first connection member and the second connection member.
However, the ordinary artisan would have recognized the height of the oxide layer to be a result effective variable affecting how the growth of the oxide layer is controlled (paragraph 0020) Thus, it would have been obvious to set the heights of the oxide layer and the connection members within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. in view of Oh et al. (US 20110068151 A1).
Regarding claim 7, Chem teaches the semiconductor package of claim 1. Chen et al. does not teach the package further comprising a barrier layer surrounding the third surface and a side surface of the second connection member.
FIG. 6A and FIG. 6B of Oh et al. teach first and second materials (130; FIG. 6A; FIG. 6B; paragraph 0107) and (140; FIG. 6A; FIG. 6B; paragraph 0107) may cover an outer surface of the entire solder ball (115; FIG. 6A; FIG. 6B; paragraph 0107) and pad (121; FIG. 6A; FIG. 6B; paragraph 0107).
Chen et al. and Oh et al. are both analogous to the claimed invention in that they involve semiconductor packages with two structures connected by members. Therefore, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen et al. so that the package further comprises a barrier layer surrounding the third surface and a side surface of the second connection member. These material coatings are key for adhesion for the connection members.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. in view of Oh et al. and in further view of Hsiao et al. (US 20110101526 A1).
Regarding claim 8, the combination of Chen et al. in view of Oh et al. teach the semiconductor package of claim 7. Neither Chen et al. nor Oh et al. teach the barrier layer including nickel (Ni).
Hsiao et al. teaches that a barrier layer (36; FIG. 2; paragraph 0022) may be formed of nickel.
Chen et al, Oh et al., and Hsiao et al. are all analogous to the claimed invention in that they involve semiconductor packages with two structures connected by members. Therefore, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen et al. so that the barrier layer includes nickel. Nickel is a known metal used in barriers (paragraph 0022).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. in view of Zarbock et al. (US 20100078799 A1).
Claim 9 would be allowable as Chen et al. teaches the semiconductor package of claim 1. Chen et al. does not teach the package further comprising an interface layer between the second surface of the first connection member and the third surface of the second connection member, wherein the interface layer includes SnBi and SAC.
FIG. 7 of Chen et al. teaches a solder paste (38; FIG. 7; paragraph 0020) made of tin-silver-copper and tin bismuth and set between substrate pads (34; FIG. 7; paragraph 0020) and carbon nanotubes (44; FIG. 7; paragraph 0021).
Chen et al. and Zarbock et al. are both analogous to the claimed invention in that they involve semiconductor devices with members connecting two structures. Therefore, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen et al. to have an interface layer between the second surface of the first connection member and the third surface of the second connection member, wherein the interface layer includes SnBi and SAC. These materials are known to form highly conductive adhesives (paragraph 0020).
Allowable Subject Matter
Claims 11-16 would be allowable if the aforementioned objection for claim 11 is corrected.
Claim 11 would be allowable as Yoon (US 20160118337 A1 teaches a semiconductor package (100; FIG. 1; paragraph 0035) comprising:
a first structure (100; FIG. 1; paragraph 0035) including:
a plurality of first vias (141; FIG. 1; paragraph 0039);
a plurality of first metal pads (151-1; FIG. 1; paragraph 0039) on the plurality of first vias;
a first insulation layer (121; FIG. 1; paragraph 0040) surrounding the plurality of first vias; and
a second insulation layer (121; FIG. 1; paragraph 0040) disposed on the first insulation layer and including a plurality of openings.
Yoon does not teach a second structure including:
a third insulation layer;
a plurality of second metal pads on the third insulation layer;
a plurality of second vias on the plurality of second metal pads; and
a fourth insulation layer surrounding the plurality of second metal pads and the plurality of second vias;
a plurality of first connection members including SnBi; and
a plurality of second connection members including SAC (Sn, Ag and Cu),
wherein a first surface of each first connection member of the plurality of first connection members is bonded to a corresponding first metal pad of the plurality of first metal pads through a corresponding opening of the plurality of openings,
each second connection member of the plurality of second connection members penetrates the third insulation layer, for each first connection member, a second surface of the first connection member opposite the first surface of the first connection member is bonded to a third surface of a corresponding one of the plurality of second connection members, and for each second connection member of the plurality of second connection members, a fourth surface opposite the third surface of the [sic] is bonded to a corresponding second metal pad of the plurality of second metal pads,
the third surface of each second connection member of the plurality of second connection members is flat, and
a diameter in a horizontal direction of each second connection member of the plurality of second connection members decreases in a direction receding from the third surface.
FIG. 44 and FIG. 45 of Chen et al. teaches a second semiconductor chip (710; FIG. 44; paragraph 0085), a bump comprising a tin-bismuth alloy as a first connection member (620; FIG. 44; paragraph 0086), where the first surface is attached to an under-bump-metallurgy layer (640; FIG. 44; paragraph 0086), connecting pads comprising a tin-silver-copper alloy (760; FIG. 44; paragraph 0091) with a flat third surface (FIG. 44) and a fourth surface attached to a under-bump-metallurgy layer (770; FIG. 44; paragraph 0091), where the diameter decreases further from the third surface (760; FIG. 49; paragraph 0097), with a second surface of the bump and the third surface of the connecting member attached (FIG. 45).
Chen et al. does not teach a third insulation layer;
a plurality of second metal pads on the third insulation layer;
a plurality of second vias on the plurality of second metal pads;
a fourth insulation layer surrounding the plurality of second metal pads and the plurality of second vias;
and each second connection member of the plurality of second connection members penetrates the third insulation layer.
Therefore, it would be improper in hindsight to modify Yoon to have the second vias, the third insulation layer allowing the second connection members, the metal pads within the third insulation layer, and the fourth insulation layer surrounding the vias.
Claims 12-16 would be allowable as they are dependent on claim 11.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hino et al. (US 20180229333 A1) concerns a solder paste and mount structure for semiconductor devices. Maki (US 20080316721 A1) concerns an electrode body structure that includes a tin/nickel solder alloy layer..
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A VLCEK whose telephone number is (571)272-9665. The examiner can normally be reached Mon-Fri, 9:00 AM -5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/J.A.V./ Examiner, Art Unit 2817
/RATISHA MEHTA/ Primary Examiner, Art Unit 2817