Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment under 37 CFR 1.132 filed June 5th, 2026 is sufficient to overcome the rejection of claim 1 based upon 35 U.S.C. 102(a)(1).
The amendment under 37 CFR 1.132 filed June 5th, 2026 is sufficient to overcome the objection of claim 11.
All other amendments filed June 5th, 2026 are acknowledged and accepted.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 3, 10, 21, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20060220259 A1).
Regarding claim 1, FIG. 44 and FIG. 49 of an embodiment of Chen et al. teach a semiconductor package (paragraph 0017) comprising:
a first structure (610; FIG. 44; paragraph 0085);
a second structure (710; FIG. 44; paragraph 0085);
a plurality of first connection members including SnBi (620; FIG. 44; paragraph 0086); and
a plurality of second connection members including SAC (Sn, Ag and Cu) (760; FIG. 44; paragraph 0091),
wherein each first connection member has a first surface (620; FIG. 44; paragraph 0086) and a second surface (620; FIG. 44; paragraph 0086) opposite each other, and the first surface is bonded to the first structure,
wherein each second connection member has a third surface (760; FIG. 44; paragraph 0091) bonded to the second surface of a respective first connection member, a fourth surface (760; FIG. 44; paragraph 0091) opposite the third surface and bonded to the second structure, and a side surface (760; FIG. 44; paragraph 0091) extending from the third surface toward the second structure
wherein the third surface of each second connection member is flat, and
wherein a diameter of each second connection member (760; FIG. 49; paragraph 0097) decreases in a direction receding from the third surface of each second connection member.
This specific embodiment of Chen et al. does not teach the package wherein the side surface of each second connection member does not contact the respective first connection member bonded thereto. However, FIG. 7 of another embodiment of Chen et al. teaches conductive pillars (230; FIG. 7; paragraph 0049) attached to the top of connecting blocks (241; FIG. 7; paragraph 0049) without either of their side surfaces contacting the other.
It would have been obvious to modify the first embodiment of Chen et al. to have the side surface of each second connection member not contacting the respective first connection member bonded thereto. This is a known aspect of the embodiment that the connection only needs to cover one side (paragraph 0049).
Regarding claim 2, Chen et al. teaches the semiconductor package of claim 1. Chen et al. does not teach an angle between a bottom surface of the second structure and the side surface of each second connection member being 60o to 80o as the angle cannot be exactly measured (FIG. 46).
However, the ordinary artisan would have recognized the 60o to 80o angle measurement to be a result effective variable affecting how the second connection members (760; FIG. 46: paragraph 0091) fit into the bump pads (753; FIG. 46: paragraph 0091) on the second structure (710; FIG. 46; paragraph 0085). Thus, it would have been obvious to set the angle within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B.
Regarding claim 3, Chen et al. teaches the semiconductor package of claim 1. FIG. 44 of Chen et al. further teaches the package further comprising an under-bump structure (770; FIG. 44; paragraph 0091) between the plurality of second connection members (760; FIG. 44; paragraph 0091) and the second structure (710; FIG. 44; paragraph 0085).
Regarding Claim 10, Chen et al. teaches the semiconductor package of claim 1. Chen et al. does not explicitly display a volume ratio of each first connection member to the respective second connection member to which the first connection member is bonded being 0.4:1 to 0.5:1.
However, the ordinary artisan would have recognized the volumes of the connection members to be a result effective variable affecting the connection method (paragraph 0093). Thus, it would have been obvious to set the volume ratio within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B.
Regarding claim 21, Chen et al. teaches the semiconductor package of claim 1. Chen et al. further teaches the package wherein:
each of the plurality of first connection members (620; FIG. 44; paragraph 0086) is spaced apart from the second structure (710; FIG. 44; paragraph 0085).
Regarding claim 22, Chen et al. teaches the semiconductor package of claim 1. The first embodiment of Chen et al. does not teach the package wherein:
the plurality of first connection members and the plurality of second connection members do not overlap in a direction that is parallel to the third surface.
However, FIG. 7 of another embodiment of Chen et al. teaches conductive pillars (230; FIG. 7; paragraph 0049) attached to the top of connecting blocks (241; FIG. 7; paragraph 0049) on surfaces that make contact but otherwise don’t overlap.
It would have been obvious to modify the first embodiment of Chen et al. to have the plurality of first connection members and the plurality of second connection members not overlap in a direction that is parallel to the third surface. This is the result of the connecting blocks only contacting one side of the conductive pillar (paragraph 0049).
Claims 4, 5, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. in view of Terishima et al. (US 20120223430 A1).
Regarding claim 4, Chen et al. teaches the semiconductor package of claim 1. Chen et al. does not teach the package further comprising an oxide layer on the side surface of each second connection member.
Terishima teaches an oxide layer (paragraph 0019) formed on a Sn-Ag-Cu solder ball surface (paragraph 0010).
Chen et al and Terishima et al. are both analogous to the claimed invention in that they involve semiconductor packages with connection members. Therefore, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen et al. so that the package further comprises an oxide layer on the side surface of each second connection member. This is because the growing oxide layer on the solder ball is a natural phenomenon
Regarding claim 5. Chen et al. teaches the semiconductor package of claim 4. Chen et al. does not teach the oxide layer including at least one of: Sn oxide, Ag oxide and Cu oxide.
Terishima teaches forming a non-crystalline tin-oxide layer over the solder ball surface (paragraph 0019).
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen et al. so that the oxide layer includes at least an Sn oxide. This is because keeps the oxide layer from growing uncontrollably (paragraph 0019).
Regarding claim 6, the combination of Chen et al. in view of Terishima et al. teaches the semiconductor package of claim 4. Neither Chen et al. nor Terishima et al. teach the package wherein for each second connection member, the oxide layer having a height greater than 30% of a sum of heights of the respective second connection member and the first connection member bonded thereto.
However, the ordinary artisan would have recognized the height of the oxide layer to be a result effective variable affecting how the growth of the oxide layer is controlled (paragraph 0020) Thus, it would have been obvious to set the heights of the oxide layer and the connection members within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. in view of Oh et al. (US 20110068151 A1).
Regarding claim 7, Chen et al. teaches the semiconductor package of claim 1. Chen et al. does not teach the package wherein each second connection member further comprises a barrier layer surrounding the third surface and the side surface of the respective second connection member.
FIG. 6A and FIG. 6B of Oh et al. teach first and second materials (130; FIG. 6A; FIG. 6B; paragraph 0107) and (140; FIG. 6A; FIG. 6B; paragraph 0107) may cover an outer surface of the entire solder ball (115; FIG. 6A; FIG. 6B; paragraph 0107) and pad (121; FIG. 6A; FIG. 6B; paragraph 0107).
Chen et al. and Oh et al. are both analogous to the claimed invention in that they involve semiconductor packages with two structures connected by members. Therefore, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen et al. so that each second connection member further comprises a barrier layer surrounding the third surface and the side surface of the respective second connection member. These material coatings are key for adhesion for the connection members (paragraph 0014).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. in view of Oh et al. and in further view of Hsiao et al. (US 20110101526 A1).
Regarding claim 8, the combination of Chen et al. in view of Oh et al. teach the semiconductor package of claim 7. Neither Chen et al. nor Oh et al. teach the barrier layer including nickel (Ni).
Hsiao et al. teaches that a barrier layer (36; FIG. 2; paragraph 0022) may be formed of nickel.
Chen et al, Oh et al., and Hsiao et al. are all analogous to the claimed invention in that they involve semiconductor packages with two structures connected by members. Therefore, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen et al. so that the barrier layer includes nickel. Nickel is a known metal used in barriers (paragraph 0022).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. in view of Zarbock et al. (US 20100078799 A1).
Claim 9 would be allowable as Chen et al. teaches the semiconductor package of claim 1. Chen et al. does not teach the package further comprising an interface layer between the third surface of each second connection member and the second surface of the respective first connection member bonded thereto, wherein the interface layer includes SnBi and SAC.
FIG. 7 of Chen et al. teaches a solder paste (38; FIG. 7; paragraph 0020) made of tin-silver-copper and tin bismuth and set between substrate pads (34; FIG. 7; paragraph 0020) and carbon nanotubes (44; FIG. 7; paragraph 0021).
Chen et al. and Zarbock et al. are both analogous to the claimed invention in that they involve semiconductor devices with members connecting two structures. Therefore, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen et al. to have an interface layer between the third surface of each second connection member and the second surface of the respective first connection member bonded thereto, wherein the interface layer includes SnBi and SAC. These materials are known to form highly conductive adhesives (paragraph 0020).
Allowable Subject Matter
Claims 11-16 would be allowable if the aforementioned objection for claim 11 is corrected.
Regarding claim 11, Yoon (US 20160118337 A1 teaches a semiconductor package (100; FIG. 1; paragraph 0035) comprising:
a first structure (100; FIG. 1; paragraph 0035) including:
a plurality of first vias (141; FIG. 1; paragraph 0039);
a plurality of first metal pads (151-1; FIG. 1; paragraph 0039) on the plurality of first vias;
a first insulation layer (121; FIG. 1; paragraph 0040) surrounding the plurality of first vias; and
a second insulation layer (121; FIG. 1; paragraph 0040) disposed on the first insulation layer and including a plurality of openings.
Yoon does not teach a second structure including:
a third insulation layer;
a plurality of second metal pads on the third insulation layer;
a plurality of second vias on the plurality of second metal pads; and
a fourth insulation layer surrounding the plurality of second metal pads and the plurality of second vias;
a plurality of first connection members including SnBi; and
a plurality of second connection members including SAC (Sn, Ag and Cu),
wherein a first surface of each first connection member of the plurality of first connection members is bonded to a corresponding first metal pad of the plurality of first metal pads through a corresponding opening of the plurality of openings,
wherein each second connection member of the plurality of second connection members penetrates the third insulation layer,
wherein, for each first connection member, a second surface of the first connection member opposite the first surface of the first connection member is bonded to a third surface of a corresponding one of the plurality of second connection members,
wherein, for each second connection member of the plurality of second connection members, a fourth surface of the second connection member opposite the third surface is bonded to a corresponding second metal pad of the plurality of second metal pads,
wherein the third surface of each second connection member of the plurality of second connection members is flat, and
wherein a diameter in a horizontal direction of each second connection member of the plurality of second connection members decreases in a direction receding from the third surface thereof.
FIG. 44 and FIG. 45 of Chen et al. teaches a second semiconductor chip (710; FIG. 44; paragraph 0085), a bump comprising a tin-bismuth alloy as a first connection member (620; FIG. 44; paragraph 0086), where the first surface is attached to an under-bump-metallurgy layer (640; FIG. 44; paragraph 0086), connecting pads comprising a tin-silver-copper alloy (760; FIG. 44; paragraph 0091) with a flat third surface (FIG. 44) and a fourth surface attached to a under-bump-metallurgy layer (770; FIG. 44; paragraph 0091), where the diameter decreases further from the third surface (760; FIG. 49; paragraph 0097), with a second surface of the bump and the third surface of the connecting member attached (FIG. 45).
Chen et al. does not teach a third insulation layer;
a plurality of second metal pads on the third insulation layer;
a plurality of second vias on the plurality of second metal pads;
a fourth insulation layer surrounding the plurality of second metal pads and the plurality of second vias;
and each second connection member of the plurality of second connection members penetrates the third insulation layer.
None of the located prior art teaches this limitation. Therefore, it would be improper in hindsight to modify Yoon to have the second vias, the third insulation layer allowing the second connection members, the metal pads within the third insulation layer, and the fourth insulation layer surrounding the vias.
Claims 12-16 would be allowable as they are dependent on claim 11.
Claim 23 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 23, Chen et al. teaches the semiconductor package of claim 1. Chen et al. does not teach the semiconductor package wherein:
the second structure includes an insulation layer,
the plurality of second connection members extend through the insulation layer, and
each first connection member is spaced apart from the insulation layer.
Yoon et al. teaches a semiconductor structure including multiple insulation layers (121; FIG. 1; paragraph 0040). Yoon et al. does not teach the package wherein:
the plurality of second connection members extend through the insulation layer, and
each first connection member is spaced apart from the insulation layer.
FIG. 9 of Kim et al. (US 20190198486 A1) teaches an insulating layer (111; FIG. 9; paragraph 0082) that is separated from a copper layer (226; FIG. 9; paragraph 0102) of a conductive bump (228; FIG. 9; paragraph 0102). Kim et al. does not teach the plurality of second connection members extending through the insulation layer.
None of the located prior art teach this limitation. Therefore, it would be improper in hindsight to modify Chen et al. to have the plurality of second connection members extend through the insulation layer, and each first connection member is spaced apart from the insulation layer.
Response to Arguments
Applicant’s arguments with respect to the amended claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hino et al. (US 20180229333 A1) concerns a solder paste and mount structure for semiconductor devices. Maki (US 20080316721 A1) concerns an electrode body structure that includes a tin/nickel solder alloy layer.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A VLCEK whose telephone number is (571)272-9665. The examiner can normally be reached Mon-Fri, 9:00 AM -5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB ALEXANDER VLCEK/ Examiner, Art Unit 2817
/RATISHA MEHTA/ Primary Examiner, Art Unit 2817
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