Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment to claim 12 corrects the antecedent basis issue. The 112 rejection of claims 12 – 14 are withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3 – 5, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20150333173 A1 hereinafter Wu.
For claim 1, Wu teaches a non-volatile memory device (fig. 1) comprising at least one memory cell (fig. 1 numeral 100) wherein the at least one memory cell comprises: a substrate (fig. 1 numeral 102); a select gate disposed on the substrate (fig. 1 numeral 136A, 136B); a floating gate disposed on the substrate and laterally spaced apart from the select gate (fig. 1 numeral 110A, 110B), wherein the floating gate comprises a plurality of top edges (fig. 1 shows the floating gates 110A, 110B with multiple top edges); a floating gate cap layer disposed on a top surface of the floating gate (fig. 1 numeral 122A, 122B), wherein an area of a top surface of the floating gate cap layer is less than an area of a bottom surface of the floating gate (fig. 1 shows cap layers 122A and 122B having an area less than a bottom surface of the floating gates 110A and 110B); an erase gate disposed on the floating gate, wherein one or more of the plurality of top edges are embedded with the erase gate (fig. 1 numeral 138 shows the erase gate surrounding at least one of the top edges of the floating gate; fig. 5D shows erase gate 526 surrounding at least one top edge of the floating gate 110); and a control gate covered with the erase gate, wherein the floating gate is disposed between the control gate and the select gate (fig. 1 numeral 116A, 116B; fig. 5D numeral 116). Wu is silent regarding the floating gate comprising a plurality of top edges forming a closed shape as viewed from a top-down perspective. However, Wu does teach the floating gate comprising top edges (fig. 1 shows floating gate 110 having at least two edges at the top surface) and that the shape of the floating gate is shown to be continuous and without breaks, forming a closed shape (fig. 1 numeral 110, fig. 5D numeral 110). Examiner is interpreting the term “embedded” given the broadest reasonable interpretation as to mean enclosed closely in or set firmly into a mass or material. Applicant states that paragraph [0035] of the immediate invention supports the use of the term embedded, but the term embedded does not appear in the specification so examiner has given embedded the broadest reasonable interpretation. As the floating gate 110A in figure 1 appears to be enclosed or set firmly into the erase gate 138, the floating gate appears to be embedded with the erase gate.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention that the top edges of the floating gate would form a closed shape when viewed from a top-down perspective, as Wu appears to teach the floating gate including top edges with a closed shape and a change in orientation would result in a closed shape when viewed from a top-down perspective as such modification would involve a mere change in configuration. It has been held that a change in configuration of shape of a device is obvious, absent persuasive evidence that a particular configuration is significant. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
For claim 3, Wu teaches all of claim 1. Wu also teaches the floating gate comprises two sidewalls disposed opposite each other (fig. 1 numeral 110A, 110B) and each of the sidewalls is partially covered with the select gate (fig. 1 shows select gate 136A, 136B on either side of floating gate 110A and 110B, resulting in the select gate covering both sides of the floating gate). Examiner is interpreting “partially covered” to mean to overlap in an orientation, and not requiring direct contact between the two objects. Claim 1 does not appear to require direct contact between the floating gate and the select gate and does not state the orientation that the covering occurs in.
For claim 4, Wu teaches all of claim 3. Wu also teaches a dielectric spacer disposed between each of the sidewalls and the select gate (fig. 1 numeral 134A, 134B).
For claim 5, Wu teaches all of claim 1. Wu also teaches an inter-gate dielectric layer (fig. 1 numeral 114A, 114B) and a top surface of the inter-gate dielectric layer is lower than the plurality of top edges. Wu does not show a top-down perspective of the device.
One of ordinary skill in the art before the effective filing date of the immediate invention would recognize the inter-gate dielectric layers as having a configuration that surrounds the floating gate if viewed from a top-down perspective, as the dielectric is shown to be wider that the floating gate, is shown formed to be around the base of the floating gate (fig. 3F numeral 302 being the layer that forms the inter-gate dielectric and numeral 304 being the floating gate layer; fig. 3G shows after etching the integrate dielectric is wider than the floating gate), and that it would be obvious to form the inter-gate dielectric surrounding the floating gate as such modification would involve a mere change in configuration. It has been held that a change in configuration of shape of a device is obvious, absent persuasive evidence that a particular configuration is significant. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
For claim 17, Wu teaches all of claim 1. Wu also teaches the plurality of top edges are covered with and electrically coupled to the erase gate (fig. 1 shows erase gate 138A and 138B covering and electrically connected to the top edges of the floating gate 110A; Par. [0013 - 0017]).
Claim(s) 8 – 10, and 15 – 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20150333173 A1 hereinafter Wu in further view of US 20190148504 A1 hereinafter Chu.
For claim 8, Wu teaches all of claim 1. Wu is silent regarding the top surface of the floating gate further comprises a center region lower than the plurality of top edges.
Chu teaches a memory device (Chu, fig. 2) with a floating gate (fig. 2 numeral 212) that includes a center region lower than the plurality of top edges of the floating gate (fig. 2 numeral t1 and t1* show a center region lower than the top edges of the floating gate).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the center region in Chu with the floating gate in Wu in order to enhance the coupling ration between the floating gate and control gates (Chu, Par. [0026]) and assist in creating the uniformity of the device (Chu, Par. [0026]).
For claim 9, Wu and Chu teach all of claim 8. Chu also teaches the floating gate comprising a top tip surrounding the center region of the top surface of the floating gate (Chu, fig. 2 numeral 212). Wu and Chu do not show a top-down perspective.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention that the floating gate in Wu and Chu would comprise a top tip surrounding the center region of the top surface of the floating gate if viewed from a top-down perspective, as Chu teaches the floating gate including a top surface with portions higher than the center portion that are on either side of the center portion, resulting in the top surface surrounding the center portion and would appear to be surrounding the center portion if the device is rotated to be viewed from the top-down perspective.
For claim 10, Wu and Chu teach all of claim 9. Chu also teaches a floating gate cap layer (Chu, fig. 2 numeral 214) that includes a lowermost portion (fig. 2 shows the lowermost portion at height t1*) that is surrounded by the top tip of the floating gate (fig. 2 numeral 212 at height t1). Wu and Chu do not show a top-down perspective of the device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention that the floating layer in Wu and Chu would comprise a top tip of the floating gate surrounding the lowermost portion of the floating gate cap layer if viewed from a top-down perspective, as Chu teaches the floating gate including a top surface with portions higher than the lowermost portion of the floating gate cap layer that are on either side of the floating gate cap layer, resulting in the top surface surrounding the lowermost portion of the floating gate cap layer and would appear to be surrounding the lowermost portion if the device is rotated to be viewed from the top-down perspective.
For claim 15, Wu teaches all of claim 1. Wu is silent regarding the top surfaces of the floating gate cap layer being lower than one or more of the plurality of top edges.
Chu teaches A memory device (Chu, fig. 2) with a floating gate with top edges (fig. 2 numeral 212) and floating gate cap layer (fig. 2 numeral 214) and a top surface of the floating cap layer is lower than one or more of the plurality of top edges (fig. 2 shows top edges at height t1 and the top surface of the floating gate cap layer at height t1*).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the floating gate cap layer and top edges of the floating gate in Chu with the floating gate and control gate in Wu in order to improve coupling between the gates and other layers (Chu, Par. [0026]).
For claim 16, Wu and Chu teach all of claim 15. Wu also teaches the top surface of the floating gate cap layer being covered with the erase gate (Wu, fig. 1 numeral 138; fig. 5D numeral 526).
Allowable Subject Matter
Claims 2, 6 – 7, and 11 – 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
For claim 2, Wu and Chu are silent regarding the plurality of top edges of the floating gate are higher than a top surface of the select gate. Wu teaches the select gate 136A and 136B of figure 1 as having top surfaces higher than the floating gate 110A and 110B.
For claim 6, Wu and Chu are silent regarding the inter gate dielectric layer covering a top surface of the select gate and a top surface of the control gate. Specifically, the select gate in Wu is shown to be free of any layer over the top surface of the select gate (Wu, fig. 5D numeral 524).
For claim 7, Wu and Chu are silent regarding the erase gate dielectric covering the top surface of the select gate. Specifically, the select gate in Wu is shown to be free of any layer over the top surface of the select gate (Wu, fig. 5D numeral 524).
For claim 11, Wu and Chu teach all of claim 8. Wu and Chu are silent regarding the top edges including four top edges, two being the two first top edges and the other two being the second top edges, and wherein the first top edges and the second top edges are higher than the center region of the top surface of the floating gate. Chu teaches the top edges being higher than the center region of the top surface of the floating gate, but only shows two top edges and does not appear to teach at least four top edges being present higher than the center region of the top surface of the floating gate.
For claim 12, Wu teaches all of claim 1. Wu teaches the control gate not being shared and instead each memory cell has its own control gate (Wu, fig. 1 numeral 110A and 110B). This appears to teach away from the shared control gate as interpreted by the examiner in claim 12 of the immediate invention.
Claims 13 – 14 are allowable as depending on an allowable claim but are objected to for depending on a rejected base claim.
Response to Arguments
Applicant's arguments filed 03/23/2026 have been fully considered but they are not persuasive.
Applicant’s argument directed to claim 1 is not persuasive as the prior art appears to teach the structural limitations present in claim 1. Applicant’s arguments that the method taught in Wu teach away from embedded structure as claimed is not persuasive as the structural limitations as claimed in the immediate invention appear substantially identical to the structure in Wu. Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). Claim 1 only requires one of the top edges of the plurality of top edges of the floating gate is embedded with the erase gate. Wu appears to show in figure 1 that the erase gate 138 at least surrounds and is over one of the top edges of the floating gate 110A or 110B. Similarly, figure 5D shows an embodiment wherein the erase gate 526 surrounds and is over at least one top edge of the floating gate 110. See the rejection of claim 1 above. As the structural limitations in the immediate invention appear to be met by the prior art Wu, a prima facie case of either anticipation or obviousness has been established.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.T.N./Examiner, Art Unit 2815
/MONICA D HARRISON/Primary Examiner, Art Unit 2815
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