DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed on 07/27/2023 has been considered and
placed in the application file.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-14 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over La Grou (U.S. 20116/03454401)
Regarding claim 1, La Grou (hereinafter, Ref~401) discloses (pleases see 3A and related text for details) a method of feedback control of an amplifier system (300 of Fig. 3A), the method comprising:
driving multiple amplifier circuits (305/306 of Fig. 3A) using at least one digital-to-analog converter (DAC) circuit (303 and/or 304 of Fig. 3A) to set a system output of the amplifier system;
operating the at least one DAC circuit using a first set of DAC codes to set (via DSP 302 of Fig. 3A) the system output to a steady state target output (please note paragraph [0072] for details related to the claimed steady stage signals);
detecting (via feedback feature centered by ADC 320 and/or 325 and/or 330 of Fig. 3A) a high glitch condition at an output of the at least one DAC circuit when using the first set of DAC codes (Specifically, Ref~648 teaches that the ADC level reporting is used by the DSP (302) to control the level of the output signals (333) and (334) to compensate for normal passive level losses and other losses or changes in output level as described in paragraph [0070], thus supporting the broadly claimed glitch condition); and
changing (via output control signals from DSP 302 of Fig. 3A) to operating the at least one DAC circuit using a second set of DAC codes (provided by said DSP 302 of Fig. 3A) to set the system output to substantially the same steady state target output, wherein operating the at least one DAC circuit using the second set of DAC codes reduces glitch energy at the output of the least one DAC circuit. Ref~401 teaches that the present invention to provide method and apparatus for digital-to-analog conversion which utilizes circuit behavior monitoring and feedback to improve performance characteristics as described in paragraph [0072-0074]) including glitch-free as described in paragraph [0054], meeting claim 1.
Regarding claim 2, Ref~401 supports the claimed “wherein detecting the high glitch condition includes detecting (via feedback features as descried above) a high-energy glitch transition that is greater than a threshold glitch transition when operating the at least one DAC circuit using the first set of DAC codes as described in paragraph [0074] via comparison disclosed, meeting claim 2.
Regarding claim 3, Ref~401 supports the claimed” wherein detecting the high glitch condition includes identifying that the first set of DAC codes includes a DAC code transition associated with the high glitch condition when setting the system output to the steady state target output”, since it is configured and operate in the same manner compared to the claimed one due to the dynamic feedback features of Fig. 3A, meeting claim 3.
Regarding claim 4, Ref~401 discloses the method of claim 1, including:
setting the system output to the steady state target output using a control loop that includes a feedback circuit path (provided through ADC 320 and/or 324 and/or 330 of Fig. 3A); and
wherein the changing to operating the at least one DAC circuit using a second set of DAC codes (provided via DSP 302 of Fig. 3A) includes adding an offset to the control loop to operate the at least one DAC circuit using the second set of DAC codes as described in paragraph [0074], meeting claim 4.
Regarding claim 5, Ref~401 supports the claimed “wherein the adding the offset to the control loop includes adding a programmable offset to the control loop using another DAC circuit”, since the DSP calculate the amount of compensations required based on measurements as described in paragraph [0068], meeting claim 5.
Regarding claim 6, Ref~401 discloses the method of claim 1, including:
applying an output of the at least one DAC circuit to an input of a first amplifier circuit (305 or 306 of Fig. 3A) and an input of a second amplifier circuit (306 or 305 of Fig. 3A) of the multiple amplifier circuits when operating the amplifier system in a first mode (e.g., during high gain mode provided by high path amplifier 305 of Fig. 3A); and
applying the output of the at least one DAC circuit to the input of the first amplifier circuit and applying an output of another DAC circuit to the input of the second amplifier circuit in a second mode (e.g., during low gain mode provided by the low path amplifier 306 of Fig. 3A), wherein the second mode has a lower voltage output than the first mode, meeting claim 6.
Regarding claim 7, Ref~401 discloses the method of claim 1, wherein the driving the multiple amplifier circuits includes:
driving multiple DAC channels (at least two channels are shown in the embodiment of Fig. 3A), wherein each DAC channel includes a main DAC and an amplifier circuit, and the amplifier circuits of the DAC channels have different signal gain as described above;
operating the main DAC circuits of the DAC channels using the first set of DAC codes and summing outputs of the DAC channels (via 360 of Fig. 3A) to set the system output; and
using a control loop (centered by ADCs 320/325/330 of Fig. 3A) to set the system output to the steady state target output and to change to operating the main DAC circuits using the second set of DAC codes to reduce ripple of the system output caused by the multiple DAC channels, meeting claim 7.
Regarding claim 8, Ref~401 discloses the method of claim 7, including:
detecting (via feedback features of Fig. 3A) a high-energy glitch transition that is greater than a threshold glitch transition when operating the at least one DAC circuit using the first set of DAC codes (see paragraph [0074]);
determining (via DSP 302 of Fig. 3A) an offset using a magnitude of the high-energy glitch transition and current DAC code; and
selecting (via DSP 302 of Fig. 3A) a set of DAC codes as the second set of DAC codes using the determined offset, meeting claim 8.
Regarding claim 9, Ref~401 discloses the method of claim 1, including:
updating (via DSP 302 of Fig. 3A) a DAC code of the at least one DAC circuit using DAC code values selected from the first set of DAC codes to set the system output to the steady state target output;
detecting (via feedback features from Fig. 3A) when the DAC code of the at least one DAC circuit settles near a high-glitch DAC code transition when setting the system output to the steady state target output; and
updating (via DSP of Fig. 3A) the DAC code of the at least one DAC circuit using DAC code values selected from the second set of DAC codes in response to the detecting, meeting claim 9.
Regarding claim 10, Ref~401 discloses (e.g., please see Fig. 3A and related text for details) an amplifier system (300 of Fig. 3A) including:
at least one digital to analog converter (DAC) circuit (303 and/or 304 of Fig. 3A), wherein setting (via DSP 302 of Fig. 3A) a DAC code in the at least one DAC circuit sets an output of the at least one DAC circuit;
multiple amplifier circuits (305/306 of Fig. 3A) including inputs connected to the output of the at least one DAC circuit;
a feedback circuit path (centered by 320 of Fig. 3A) connected to a system output (365 of Fig. 3A) of the amplifier system; and
a control circuit (DSP 302 of Fig. 3A can be read as the claimed circuit OR at least it is functionally equivalent to it) connected to the at least one DAC circuit and the feedback circuit path, wherein the control circuit is configured to:
operate the at least one DAC circuit using a first set of DAC codes to set the system output to a steady state output target; and
change to operating the at least one DAC circuit using a second set of DAC codes to maintain the same steady state output target and to reduce ripple at the system output caused by the at least one DAC circuit, meeting claim 10.
Regarding claim 11, Ref~401 discloses the amplifier system of claim 10, including:
a control loop (feedback loop provided via ADC 320 of Fig. 3A) that includes the feedback circuit (centered by 320 of Fig. 3A) and the control circuit (DSP 302 of Fig. 3A);
wherein the control circuit is configured to:
detect a high glitch transition of the first set of DAC codes that is greater than a threshold glitch transition as described in paragraph [0074]; and
add an offset to the control loop to change to the selecting the DAC code from the second set of DAC codes as described in paragraph [0074], meeting claim 11.
Regarding claim 12, Ref~401 discloses the amplifier system of claim 11, including:
another DAC circuit (e.g., 304 of Fig. 3A) to add the offset to the control loop; and
wherein the control circuit is configured to set the offset according to a magnitude of the high glitch transition and one or more DAC codes values corresponding to the high glitch transition as described in paragraph [0074], meeting claim 12.
Regarding claim 13, Ref~401 discloses the amplifier system of claim 11, including:
a summing node (360 of Fig. 3A) connected to outputs of the multiple amplifier circuits as seen;
wherein the at least one DAC circuit includes multiple DAC circuits (303/304 of Fig. 3A);
wherein the inputs of the multiple amplifier circuits are connected to the outputs of the multiple DAC circuits to form multiple DAC channels and the outputs of the multiple amplifier circuits are connected to the summing node as seen; and
wherein the control circuit is configured to: update DAC codes of the multiple DAC circuits to maintain the steady state output target as described in paragraph [0072-0074]; and
add the offset to the summing node (360 of Fig. 3A) to change to selecting the DAC codes from the second set of DAC codes, meeting claim 13.
Regarding claim 14, Ref~401 discloses the amplifier system of the amplifier system of wherein the multiple amplifier circuits include a first amplifier circuit (e.g., 305 of Fig. 3A) and a second amplifier circuit (306 of Fig. 3A), and the at least one DAC circuit includes a first DAC circuit (303 of Fig. 3a) connected to an input of the first amplifier circuit and a second DAC circuit (304 of Fig. 3A) connected to an input of the second amplifier circuit;
wherein the control circuit is configured to: update the DAC codes of both the first DAC circuit and the second DAC circuit to apply an equal DAC output to the first amplifier circuit and the second amplifier circuit to set the system output to the steady state output target in a first mode as described in paragraph [0072-0074]; and
update the DAC code of only the first DAC circuit to set the system output to the steady state output target in a second mode, wherein the second mode has a lower output voltage range than the first mode as described above in above method claims, meeting claim 14.
Regarding claim 17, Ref~401 discloses the amplifier system of claim 10 wherein the feedback circuit path that includes an analog-to-digital converter (ADC 320 of Fig. 3A) circuit operatively coupled to the system output as seen; and
wherein the control circuit is configured to set the DAC code of the at least one DAC circuit to set a system output voltage to a steady state output target voltage as described above, meeting claim 17.
Regarding claim 18, Ref~401 discloses the amplifier system of claim 10, including:
a sense impedance (at summing node 360 of Fig. 3A) at the system output;
wherein the feedback circuit path that includes an analog-to-digital converter (ADC 320 of Fig. 3A) circuit operatively coupled to the sense impedance; and
wherein the control circuit is configured to set the DAC code of the at least one DAC circuit to set a system output current to a steady state target output current, meeting claim 18.
Regarding claims 19-20, limitations from these claims can be rejected in the same manner as described above in claims 1-14 and 17-18, since same features with similar language are being presented here, meeting claims 19-20.
Allowable Subject Matter
Claims 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HIEU P NGUYEN whose telephone number is 571-272-8577. The examiner can normally be reached on Monday-Friday 8:30AM-6:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/HIEU P NGUYEN/Primary Examiner, Art Unit 2843