DETAILED ACTION
Claims 1-18 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 3-5, 8-9, 12-14, 17-18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 10 is/are rejected under 35 U.S.C. 103a as being unpatentable over Liang et al. (US 2018/0035070) in view of Chen at al. (US 2009/0128220).
Claims 1, 10, Liang teaches An interface circuit, for use in a display device, the display device comprising:
a main board (i.e. mainboard 21) and a logic board (i.e. adapter board 23), the interface circuit comprising a video transmission interface (i.e. transmission interface), an Inter-Integrated Circuit (IIC) (i.e. i2c circuit) communication interface, and wherein the video transmission interface comprises a plurality of empty pins (i.e. unassigned pin definitions), and video signal transmission is performed between the main board and the logic board through the video transmission interface (i.e. adaptation circuit using low speed signals) (figs. 2-3; 0020-0023, 0044-0046);
the plurality of empty pins are defined as the IIC communication interface (i.e. additional customized control signals), and IIC signal transmission is performed between the main board and the logic board through the IIC communication interface (i.e. signal transmission to adaptation circuit on the adapter board using i2c) (figs. 2-3; 0020-0023, 0044-0046).
Liang is not entirely clear in teaching the specific feature of:
“an isolation circuit”;
the isolation circuit is electrically connected to the IIC communication interface.
Chen teaches the specific feature of:
“an isolation circuit” (p. 0018-0021);
the isolation circuit is electrically connected to the IIC communication interface (i.e. isolation circuit conducting the i2c signal (p. 0018-0021).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the present invention to have provided isolation circuit as taught by Chen to the system of Liang to precent circuits from influencing master circuits (p. 0021).
Claim(s) 2, 11 is/are rejected under 35 U.S.C. 103a as being unpatentable over Liang et al. (US 2018/0035070) in view of Chen at al. (US 2009/0128220), and further in view of Huang (US 2021/0020092).
Claims 2, 11, Liang is silent regarding the interface circuit according to claim 1, wherein the IIC communication interface comprises a write protection pin, a serial clock pin, and a serial data pin, the isolation circuit comprises a first isolation circuit and a second isolation circuit, the write protection pin and the serial data pin are electrically connected to the first isolation circuit, and the write protection pin and the serial clock pin are electrically connected to the second isolation circuit.
Huang teaches the interface circuit according to claim 1, wherein the IIC communication interface comprises a write protection pin (i.e. WP pin), a serial clock pin, and a serial data pin (i.e. connected to serial bus), the isolation circuit comprises a first isolation circuit and a second isolation circuit (i.e. multiple conduction elements), the write protection pin and the serial data pin are electrically connected to the first isolation circuit, and the write protection pin and the serial clock pin are electrically connected to the second isolation circuit (i.e. pins connection to serial bus) (p. 0014, 0046, 0053, 0063).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the present invention to have provided connection pins as taught by Huang to the system of Liang to provide an isolation circuit connection to a serial bus (p. 0063).
Claim(s) 6, 15 is/are rejected under 35 U.S.C. 103a as being unpatentable over Liang et al. (US 2018/0035070) in view of Chen at al. (US 2009/0128220), and further in view of Zhang et al. (US 2022/0130300).
Claims 6, 15, Liang is silent The interface circuit according to claim 1, wherein the video transmission interface further comprises a plurality of first pins, the plurality of empty pins are arranged adjacent to each other, and the first pins are arranged on two sides of the plurality of empty pins arranged adjacent to each other, and the first pins are grounded.
Zhang teaches The interface circuit according to claim 1, wherein the video transmission interface further comprises a plurality of first pins, the plurality of empty pins are arranged adjacent to each other, and the first pins are arranged on two sides of the plurality of empty pins arranged adjacent to each other, and the first pins are grounded (i.e. grounding points on opposites of transient diodes) (claim 7).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the present invention to have provided connection pins as taught by Zhang to the system of Liang to provide an connecting and grounding parts of a board (claim 7).
Claim(s) 7, 16 is/are rejected under 35 U.S.C. 103a as being unpatentable over Liang et al. (US 2018/0035070) in view of Chen at al. (US 2009/0128220), and further in view of Zhang et al. (US 2022/0130300).
Claims 7, 16, Liang is silent the interface circuit according to claim 6, wherein the video transmission interface further comprises a power supply terminal and a video transmission terminal, and the first pins and the empty pins are arranged between the power supply terminal and the video transmission terminal.
Lakkundi teaches the interface circuit according to claim 6, wherein the video transmission interface further comprises a power supply terminal and a video transmission terminal, and the first pins and the empty pins are arranged between the power supply terminal and the video transmission terminal (FIG. 3a; i.e. pins to receive power).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the present invention to have provided connection pins as taught by Lakkundi to the system of Liang to provide an power supply pins (p. 0036).
Conclusion
Claims 1-2, 6-7, 10-11, 15-16 are rejected.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20240028289 A1 LI; Cheng et al.
US 20230281527 A1 Cella; Charles H. et al.
US 20210082335 A1 SUN; LEI et al.
US 10789188 B1 Winter; Howard et al.
US 20200089183 A1 Kallikuppa; Sreenivasa Muniyappa et al.
US 20150079579 A1 Oliver; Ian James et al.
US 8638838 B1 Betts; Kevin Howard et al.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIKH I ALAM whose telephone number is (571)270-1710. The examiner can normally be reached 1:00PM-9:00PM.
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MUSHFIKH I. ALAM
Primary Examiner
Art Unit 2426
/MUSHFIKH I ALAM/ Primary Examiner, Art Unit 2426 2/4/2026