DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 5 and 19 are objected to because of the following informalities: Claim 5 cites “the serial data path” with insufficient antecedent basis requirement. Claim 19 cites “the memory access mode” with insufficient antecedent basis requirement. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4, 13, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Anderson et al. (US 2019/0126632) in view of Saida et al. (US 2019/0035449).
Regarding to claims 1, 13:
Anderson et al. discloses a print component comprising:
a plurality of memory bits (FIG. 14: The plurality of memory cells 1903-1 to 1903-n);
a first/sense contact pad located on an exterior of the print component (FIG. 13: The pad/pin BL, wherein the printhead 320 is separated from the ink fluid unit; as a result, the pad/pin BL of the control logic 1902 is not located in the printhead); and
a single lane analog bus conductively coupling the plurality of memory bits (FIG. 14: The single line (BL), connecting the memory cells to the pad/pin BL of the control logic 1902); and
wherein the first/sense contact pad transmits a single electrical signal from the plurality of memory bits, representing a parallel bit read of the plurality of memory bits (FIG. 14: The memory cells 1930 are parallelly connected to the BL pin/pad. As a result, the signal of the BL pin/pad at a certain time indicates the state of all memory cells 1930, simultaneously at that moment).
Anderson et al. however does not teach wherein the single electrical signal indicates a combination of the plurality of memory bits.
Saida et al. discloses a memory system having a memory including a plurality of cells (memory bits), wherein data of all the bit lines may be simultaneously read, charges according to the read data may be accumulated in a capacitor to output a signal (current or voltage) indicating the combination of the bit lines (paragraphs [0135] and [0136]).
Therefore, it would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to modify Anderson’s circuitry to read the memory cells, instead of sequentially, simultaneously in order to enable generating a signal that is a sum of all data read from the memory cells as taught by Saida et al. (paragraph [0135]).
Anderson et al. also discloses the following claims:
Regarding to claim 4: wherein the combination of the plurality of memory bits is further selected using a memory access mode (FIG. 14: The selection signals 1920-1 to 1920-n select the memory cells 1903 for accessing).
Regarding to claim 16: wherein the combination of the plurality of memory bits is further selected using a memory access mode enabled by programming a configuration register to address each of the combination of the plurality of memory bits to be selected (FIG. 14: The selection signals 1920-1 to 1920-n select the memory cells 1903 for accessing).
Claim(s) 21-22 and 28-29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Anderson et al. (US 2019/0126632) in view of Saida et al. (US 2019/0035449), and further in view of Shinichiro (JP 2004017529).
Anderson et al., as modified, discloses the claimed invention as discussed above except wherein the plurality of memory bits comprise non-volatile memory bits and wherein the plurality of memory bits correspond to fluid actuators proximate to nozzles of the print component.
Shinichiro discloses an inkjet printhead having a plurality of fluid actuators proximate to nozzles (Abstract: Firing nozzles, discharging nozzles) and a nonvolatile memory for storing information related to discharging nozzles (Abstract).
Therefore, it would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to modify Anderson’s printhead, as modified, to include a nonvolatile memory for storing information related to discharging nozzles as disclosed by Shinichiro (Abstract).
Allowable Subject Matter
Claims 5 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and the claim objection as discussed above is corrected.
The primary reasons for the indication of the allowability of the claims is the inclusions therein, in combination as currently claimed, of the limitation that wherein the print component is configured to select the memory bits with the memory access mode enabled by using the same input primitive and address information as used for firing fluid actuators of the print component over the serial data path is neither disclosed nor taught by the cited prior art of record, alone or in combination.
Response to Arguments
Applicant's arguments filed 3/19/2026 have been fully considered but they are not persuasive.
In response to Applicant’s assertion that Anderson’s memory cells are not for storing print component configuration data, the Examiner cites that the claim language does not define such functionality of the memory bits. In addition, the modification of Anderson in light of Saida would modify the BL line to simultaneously read the data from all memory cells and integrate the reading into a sum of currents indicating the combination of the data from all memory cells. Beside, it is conventional in a DAC circuit (Digital to Analog converter) that parallelly reading data bits stored in a memory simultaneously (in digital form) and converting the reading to a signal level to form an analog signal.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAM S NGUYEN whose telephone number is (571)272-2151.
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/LAM S NGUYEN/ Primary Examiner, Art Unit 2853
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