DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Terminal Disclaimer
The terminal disclaimer filed on 12/31/25 disclaiming the terminal portion of any patent granted on this application has been reviewed and is accepted. The terminal disclaimer has been recorded.
Claim Objections
Claims 6-7 are objected to because of the following informalities: The claims are missing in the claim submission dated 12/31/2025. Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1 and 13 are rejected under 35 U.S.C. 101 because:
Step 1: The claims, after reviewing the entire application disclosure, considered as a whole, are determined to be directed to one of the statutory category (processes, machines, manufactures, and compositions of matter): A component.
Step 2A:
Prong One: The claims recite the sequency steps of reading the plurality of memory bits in parallelly to output an electrical signal indicating the combination of the plurality of memory bits. This sequency steps as analyzed, in general just act as a digital to analog convert, so it can “practically be performed in the Human Mind” with/without sketching on paper. As stated in MPEP 2106.04(a)(2), III. Mental Processes, “A claim that encompasses a Human Performing the step(s) mentally with or without a physical aid recites a mental process”; as a result, the claim recites a mental process that falls within at least one of the abstract idea groupings (MPEP 2106.04(a) Abstract Ideas: The enumerated groupings of abstract ideas: Mathematical concepts, Certain methods of organizing human activity, Mental processes). As a result, the claims recite a judicial exception.
Prong Two: The additional steps/actions/elements recited in the claims:
- Transmitting the electrical signal from the plurality of memory bits to the contact pad via the single lane analog bus (Insignificant extra-solution activity (MPEP 2106.05(g))
When viewed in combination of as a whole, the recited additional steps/actions/elements do no more than add insignificant extra-solution to the judicial exception. As a result, these additional steps/actions/elements do not integrate the judicial exception into a practical application because they do not impose any meaningful limits on practicing the abstract idea. These claims are therefore directed to an abstract idea.
Step 2B:
The additional steps/actions/elements recited in the claims, transmitting the electrical signal from the plurality of memory bits via the contact pad via the single lane analog bus, is well known in the field as evidenced by the cited prior art addressed in the rejection below, do not amount significant to add an inventive concept to the claims because they do is no more than adding insignificant extra-solution activities to the judicial exception.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 5, and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. See MPEP § 2172.01.
Regarding to claim 1: The claim recites the limitation “a single lane analog bus conductively coupled to the plurality of memory bits” without further to define what the single lane analog bus is for.
Regarding to claims 5, 19: The claim language is unclear on how the memory bits are selected by using the input primitive and address information as for firing the print component over the serial data path.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4, 13, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Anderson et al. (US 2019/0126632) in view of Saida et al. (US 2019/0035449).
Regarding to claims 1, 13:
Anderson et al. discloses a print component comprising:
a plurality of memory bits (FIG. 14: The plurality of memory cells 1903-1 to 1903-n);
a first/sense contact pad located on an exterior of the print component (FIG. 13: The pad/pin BL, wherein the printhead 320 is separated from the ink fluid unit; as a result, the pad/pin BL of the control logic 1902 is not located in the printhead); and
a single lane analog bus conductively coupling the plurality of memory bits (FIG. 14: The single line (BL), connecting the memory cells to the pad/pin BL of the control logic 1902); and
wherein the first/sense contact pad transmits a single electrical signal from the plurality of memory bits, representing a parallel bit read of the plurality of memory bits (FIG. 14: The memory cells 1930 are parallelly connected to the BL pin/pad. As a result, the signal of the BL pin/pad at a certain time indicates the state of all memory cells 1930, simultaneously at that moment).
Anderson et al. however does not teach wherein the single electrical signal indicates a combination of the plurality of memory bits.
Saida et al. discloses a memory system having a memory including a plurality of cells (memory bits), wherein data of all the bit lines may be simultaneously read, charges according to the read data may be accumulated in a capacitor to output a signal (current or voltage) indicating the combination of the bit lines (paragraphs [0135] and [0136]).
Therefore, it would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to modify Anderson’s circuitry to read the memory cells, instead of sequentially, simultaneously in order to enable generating a signal that is a sum of all data read from the memory cells as taught by Saida et al. (paragraph [0135]).
Anderson et al. also discloses the following claims:
Regarding to claim 4: wherein the combination of the plurality of memory bits is further selected using a memory access mode (FIG. 14: The selection signals 1920-1 to 1920-n select the memory cells 1903 for accessing).
Regarding to claim 16: wherein the combination of the plurality of memory bits is further selected using a memory access mode enabled by programming a configuration register to address each of the combination of the plurality of memory bits to be selected (FIG. 14: The selection signals 1920-1 to 1920-n select the memory cells 1903 for accessing).
CONTACT INFORMATION
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAM S NGUYEN whose telephone number is (571)272-2151.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DOUGLAS RODRIGUEZ, can be reached on 571-431-0716. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAM S NGUYEN/ Primary Examiner, Art Unit 2853
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