Response to Amendment
This Office Action is in response to claim amendment filed on December 16, 2025.
Claims 1, 6, and 16 are amended.
Claims 1-23 are currently pending in this application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement received December 16, 2025; January 12, 2026 and March 20, 2026 has been considered.
Response to Arguments
The 35 U.S.C §112(b) rejection of claims 1-23 has been withdrawn in light of applicant’s
amendments and remarks (see remarks Pg. 7-9).
With respect to the prior art rejection of independent claim 1, 6, and 16 under 35 USC §103, as set forth in the previous Office Action, the claim amendment, and argument (see remarks Pg. 9-12), have been fully considered, but are not persuasive.
Applicant submits that, Gareau's timing blocks operate as detection patterns for timestamp sampling, not as control blocks containing synchronization messages to initiate handshakes. Gareau's 66b block is used as "a time reference point" where "a device should sample its local clock" and "these samples are stored locally and/or provided to a remote device for a delay and timestamp calculation." Gareau et al., paragraph [0029]. The system uses this detection to trigger timestamp sampling, where "the circuit 50 can detect the 66b block 30" to sample the local clock.
This represents a received data-block sampling mechanism, not a control block with a data portion comprising a synchronization message to initiate a synchronization handshake as recited by claims 1, 6, and 16 as amended. Gareau's approach uses the 66b block merely as a trigger for timestamp sampling, where "the time reference point is transmitted at layer one" but "does not require packet awareness, but PHY (physical) layer awareness to match a 66b pattern." Gareau et al., paragraph [0030]. Gareau's blocks do not contain a synchronization message within their data portions to initiate a handshake operation.
The examiner has considered all the arguments, but disagrees. Gareau further teaches, comprising a synchronization message to initiate a synchronization (see ¶16, ¶17, ¶19 and ¶31 wherein the transferring of PTP/timing over any layer can be performed using 66b blocks from 64b/66b encoding or a 257b blocks from 256b/257b encoding. The 66b block can be any type of control block or data block and can be used to transfer the time information. The transfer information can be 1) a time reference point, 2) the timing information itself, and (3) a measure of the delay it takes to transfer the timing information between two points and this time can be used to adjust a clock and hence is a synchronization message to initiate a synchronization).
Synchronization handshake signaling of CHEN is further incorporated to improve clock synchronization precision and security (see Pg. 4, ¶1, wherein the software time stamp is used to check the hardware time stamp so that the clock synchronization function security is satisfied and precision is improved).
As result, applicant’s arguments are not persuasive and the 35 USC §103 rejections of independent claim 1, 6, and 16 are maintained.
The 35 USC §103 rejection of dependent claims 2-5, 7-15, and 17-23, are maintained for the reasons set forth above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claim(s) 1-4, 6-10, and 12-23, are rejected under 35 U.S.C. 103 as being
Unpatentable over Gareau et al., US 20200412471 A1, (hereinafter Gareau) in view of CHEN et al., CN 118523861 A (see the English Translated copy), (hereinafter CHEN).
Regarding claim 1, Gareau teaches a system comprising:
a device coupled with a link and comprising a transmitter, the device to: generate a first control block for synchronization via a physical layer of the link (see ¶ [0024], e.g., It should be noted that both FlexE and Physical Coding Sublayer (PCS) lower part are defined as a physical link connecting two peer nodes, ¶ [0030], e.g., Advantageously, the time reference point is transmitted at layer one, the G.mtn path layer 10, as a 66b block.),
the first control block comprising a header portion of bits corresponding to a header indicating the block is a control block and a data portion of bits (see ¶ [0025], e.g., As 64b/66b encoding suggests, 64 payload bits are encoded as a 66-bit entity (a “66b block”). The first two bits of a block are the synchronization header (sync header or SH). 66b blocks are either data blocks or control blocks. The sync header is 01 for data blocks and 10 for control blocks. ¶ [0027], e.g., A 66b block 30 is highlighted in FIG. 2. The 66b block 30 includes a control character (0x4B) followed by three data characters (D1, D2, D3) followed by four zero data characters (0x000_0000)); and
transmit, via the link, the first control block comprising the header portion set of bits and the data portion of bits comprising a synchronization message to initiate a synchronization (see Fig. 4, e.g., element 102, ¶ [0037], e.g., The node A transmits a 66b block towards node B; when the 66b block for timing is detected, node A samples time T.sub.D−A; the time T.sub.D−A is transferred to the node B via a PTP message (step 102).; see ¶ [0016] e.g., the present disclosure can provide an approach for transferring PTP/timing over any layer one technique that utilizes 66b blocks (or other types of blocks such as 257b blocks from 256b/257b encoding); see ¶ [0017] e.g., The required information for the transfer of precise time is (1) a time reference point, or “significant instant” or “timestamp reference” to which timing information can be related, (2) the timing information itself, and (3) a measure of the delay it takes to transfer the timing information between two points, e.g., two devices in a network. The transfer of the precise time can be used to adjust a clock. The two devices in the network can be two network nodes or network elements.),
however, it does not explicitly teach a synchronization handshake.
CHEN teaches, a synchronization handshake (see Pg. 5, ¶3, e.g., a clock synchronization method and device, when receiving the clock synchronization signal sent by the main clock, respectively recording the first hardware time stamp and the first software time stamp through the hardware layer and the software layer of the signal transmission channel of the secondary clock; receiving the first following frame data sent by the main clock; the first following frame data comprises a second software time stamp and a second hardware time stamp respectively recorded by the software layer and the hardware layer of the signal transmission channel of the main clock when the main clock sends the clock synchronous signal; when sending the clock synchronous handshake signal to the main clock, respectively recording the third hardware time stamp and the third software time stamp through the hardware layer and the software layer of the signal transmission channel of the secondary clock;).
It would have been obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified control block of Gareau to incorporate the teachings of CHEN to include synchronization handshake signaling. Doing so would facilitate in achieving the clock synchronization with high precision and meeting the safety and security requirement as suggested by CHEN (see Pg. 4, ¶1, e.g., using the software time stamp to check the hardware time stamp so that the clock synchronization function satisfies the function security, using the software time stamp to perform the characteristic of the clock synchronization function is capable of satisfying the function security requirement, using the hardware time stamp to perform the characteristic of the clock synchronization function is high in precision, It not only satisfies the function safety requirement, but also ensures the clock synchronization with high precision, and plays an important role in the vehicle electronic system which is more and more complicated by the intelligent driving and automatic driving, and the requirement is higher and higher, which effectively ensures the performance and safety of the vehicle electronic system).
Regarding claim 2, Gareau as combined with CHEN teaches the limitations of Claim 1.
Gareau further teaches, wherein the device is further to: receive data;
parse the received data;
determine the received data is a second control block responsive to receiving the data; and store a third timestamp associated with receiving the data (see ¶ [0037], e.g., when the 66b block for timing is detected, node B samples time T.sub.D−B (step 106). When the 66b block for timing transmitted by node B is detected at node A; node A samples time T.sub.A−A; the time T.sub.A−A is transferred to node B via a PTP message (step 108).).
Regarding claim 3, Gareau as combined with CHEN teaches the limitations of Claim 2.
Gareau further teaches, wherein the device is further to:
generate a third control block for the synchronization handshake via the physical layer, the third control block comprising the header portion and a time portion indicating the third timestamp (see ¶ [0037], e.g., when the 66b block for timing is detected, node B samples time T.sub.D−B (step 106). When the 66b block for timing transmitted by node B is detected at node A; node A samples time T.sub.A−A; the time T.sub.A−A is transferred to node B via a PTP message (step 108)).
Regarding claim 4, Gareau as combined with CHEN teaches the limitations of Claim 1.
Gareau does not teach but CHEN teaches, wherein the device is further to:
receive, at a driver coupled to an application layer and the physical layer, a request to perform a synchronization handshake, wherein the request conforms to a first format (see Pg. 6, ¶5, e.g., signal 1 can be a clock synchronization signal, signal 1 is a signal generated by Timemaster and sent to Time slaver by Time master. The signal is generated by the software layer in the Timemaster, and is sent out through the Time master software layer and the hardware layer, and the process of the Time module receiving the signal 1 is as follows: The signal 1 is firstly transmitted to the hardware layer of the Time module, and then transmitted to the software layer of the Time module.);
update, at the driver, the request from the first format to a second format different than the first format; and generate the first control block responsive to updating the request from the first format to the second format (see Pg. 6, ¶7, e.g., It can be understood that the clock synchronization signal should be any signal, and the purpose of the clock synchronization signal is to trigger and record the software and hardware time stamp in the signal transmission process at the Time master and Timeslaver terminals, so the signal format and content of the clock synchronization signal can be set arbitrarily. Pg. 6, ¶8, e.g., the signal transmission should be understood as any communication format suitable for automobile products, and the signal transmission channel at least comprises one of the following: vehicle Ethernet, CAN bus, CAN FD, FLEXRAY, SPI, UART.).
It would have been obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Gareau to incorporate the teachings of CHEN to include synchronization handshake execution at a software application layer. Doing so would facilitate in achieving the clock synchronization with high precision and meeting the safety and security requirement as suggested by CHEN (see Pg. 2, ¶5, e.g., the purpose of the present application is to provide a clock synchronization method and a clock synchronization device, the hardware timestamp is verified by means of the software timestamp, so that the clock synchronization function satisfies the function security, and the clock synchronization with high accuracy can be realized while satisfying the function security requirement).
Regarding claim 6, and 16, Gareau teaches a system comprising:
a device coupled with a link and comprising a receiver and a physical layer, the device to (see ¶ [0024], e.g., It should be noted that both FlexE and Physical Coding Sublayer (PCS) lower part are defined as a physical link connecting two peer nodes; ¶ [0002], e.g., MTN fundamentally utilizes Ethernet and 64b/66b blocks. 64b/66b is a line code that transforms 64-bit data to a 66-bit line code to provide enough state changes to allow reasonable clock recovery and alignment of the data stream at the receiver.):
receive data;
parse the received data;
determine the received data is a control block responsive to receiving the data, the control block comprising a header portion of bits corresponding to a header indicating the block is a control block and a data portion of bits comprising a synchronization message to initiate a synchronization (see Fig. 4, e.g., element 104, ¶ [0037], When the 66b block for timing transmitted by node A is detected at node B, node B samples time T.sub.A−B (step 104), ¶[0005], e.g., an apparatus includes circuitry configured to detect a specific block based on a line code and to sample a clock to determine a timestamp reference based on detection of the specific block; and circuitry configured to transmit timing information based on the timestamp reference. The specific block can be a control block; see ¶ [0016] e.g., the present disclosure can provide an approach for transferring PTP/timing over any layer one technique that utilizes 66b blocks (or other types of blocks such as 257b blocks from 256b/257b encoding); see ¶ [0017] e.g., The required information for the transfer of precise time is (1) a time reference point, or “significant instant” or “timestamp reference” to which timing information can be related, (2) the timing information itself, and (3) a measure of the delay it takes to transfer the timing information between two points, e.g., two devices in a network. The transfer of the precise time can be used to adjust a clock. The two devices in the network can be two network nodes or network elements.); and
store a first timestamp associated with receiving the data (see Fig. 4, e.g., element 104, ¶[0037], When the 66b block for timing transmitted by node A is detected at node B, node B samples time T.sub.A−B (step 104). ¶ [0029], e.g., the time reference point (or timing reference point or significant instant) is a time of interest where a device should sample its local clock. These samples are stored locally and/or provided to a remote device for a delay and timestamp calculation.),
however, it does not explicitly teach a synchronization handshake via the physical layer.
CHEN teaches, a synchronization handshake via the physical layer (see Pg. 5, ¶3, e.g., a clock synchronization method and device, when receiving the clock synchronization signal sent by the main clock, respectively recording the first hardware time stamp and the first software time stamp through the hardware layer and the software layer of the signal transmission channel of the secondary clock; receiving the first following frame data sent by the main clock; the first following frame data comprises a second software time stamp and a second hardware time stamp respectively recorded by the software layer and the hardware layer of the signal transmission channel of the main clock when the main clock sends the clock synchronous signal; when sending the clock synchronous handshake signal to the main clock, respectively recording the third hardware time stamp and the third software time stamp through the hardware layer and the software layer of the signal transmission channel of the secondary clock. See Pg. 5, ¶3, e.g., Specifically, the SYNC signal is transmitted to the laser radar 402, firstly entering the physical layer Layer1, then passing through the data link layer Layer2, the laser radar 402 records the time as the first hardware time stamp t_slaver_QM according to its own clock,).
It would have been obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified control block of Gareau to incorporate the teachings of CHEN to include synchronization handshake signaling. Doing so would facilitate in achieving the clock synchronization with high precision and meeting the safety and security requirement as suggested by CHEN (see Pg. 4, ¶1, e.g., using the software time stamp to check the hardware time stamp so that the clock synchronization function satisfies the function security, using the software time stamp to perform the characteristic of the clock synchronization function is capable of satisfying the function security requirement, using the hardware time stamp to perform the characteristic of the clock synchronization function is high in precision, It not only satisfies the function safety requirement, but also ensures the clock synchronization with high precision, and plays an important role in the vehicle electronic system which is more and more complicated by the intelligent driving and automatic driving, and the requirement is higher and higher, which effectively ensures the performance and safety of the vehicle electronic system.).
Regarding claim 7, and 17, Gareau as combined with CHEN teaches the limitations of Claim 6 and 16.
Gareau further teaches, wherein the device is further to:
generate a second control block comprising the header portion of bits and a time portion of bits indicating the first timestamp and a second timestamp corresponding to storing the first timestamp (see Fig. 4, e.g., element 106, ¶ [0037], e.g., Node B transmits a 66b block towards node A; when the 66b block for timing is detected, node B samples time T.sub.D−B (step 106). ¶ [0029], e.g., the time reference point (or timing reference point or significant instant) is a time of interest where a device should sample its local clock. These samples are stored locally and/or provided to a remote device for a delay and timestamp calculation).
Regarding claim 8, and 18, Gareau as combined with CHEN teaches the limitations of Claim 7 and 17.
Gareau further teaches, wherein the device is further to:
receive second data;
parse the second data; and determine the second data is a third control block responsive to receiving the data, the third control block comprising the header portion of bits and a time portion of bits indicating a third timestamp corresponding to a second device receiving the second control block (see Fig. 4, e.g., element 106, ¶ [0037], e.g., When the 66b block for timing transmitted by node B is detected at node A; node A samples time T.sub.A−A; the time T.sub.A−A is transferred to node B via a PTP message (step 108).).
Regarding claim 9, and 19, Gareau as combined with CHEN teaches the limitations of Claim 8 and 18.
Gareau further teaches, wherein the device is to: store a fourth timestamp associated with receiving the second data (see ¶ [0037], Node B transmits a 66b block towards node A; when the 66b block for timing is detected, node B samples time T.sub.D−B (step 106). When the 66b block for timing transmitted by node B is detected at node A; node A samples time T.sub.A−A; the time T.sub.A−A is transferred to node B via a PTP message (step 108).
¶ [0029], e.g., The time reference point (or timing reference point or significant instant) is a time of interest where a device should sample its local clock. These samples are stored locally and/or provided to a remote device for a delay and timestamp calculation.).
Regarding claim 10, and 20, Gareau as combined with CHEN teaches the limitations of Claim 9 and 19.
Gareau further teaches, wherein the device is further to: execute the synchronization handshake responsive to storing the fourth timestamp (see ¶ [0037], e.g., Node B transmits a 66b block towards node A; when the 66b block for timing is detected, node B samples time T.sub.D−B (step 106). When the 66b block for timing transmitted by node B is detected at node A; node A samples time T.sub.A−A; the time T.sub.A−A is transferred to node B via a PTP message (step 108). With times T.sub.D−A, T.sub.A−B, T.sub.D−B, T.sub.A−A available at node B, the time delay between node A and node B is determined as: [00001] TIME_DELAY=R.Math.T.Math.D/2=[(TA-B-TD-A)+(TA-A-TD-B)]/2, ¶ [0038], Where RTD is the Round Trip Delay, which is [(T.sub.A−B−T.sub.D−A)+(T.sub.A−A−T.sub.D−B)]. The time error at node B is calculated as: TIME_ERROR=T.sub.A−B−(T.sub.D−A+TIME_DELAY) (step 110)).
Regarding claim 12, Gareau as combined with CHEN teaches the limitations of Claim 10.
Gareau does not teach but CHEN teaches, wherein the execution of the synchronization handshake is performed at a software application layer of the device (see Pg. 7, ¶, e.g., the application layer Layer7 of the intelligent driving domain controller 401 initiates a clock synchronization signal (marked as SYNC) and sends it, the SYNC signal is transmitted downwards in the Ethernet architecture, when passing through the transmission layer Layer4, the intelligent driving domain controller 401 records the time at this moment as the second software time stamp t1-master-ASIL according to its own clock, when passing through the data link layer Layer2, The intelligent driving domain controller 401 records the second hardware time stamp t1-master-QM at this time according to its own clock. Pg. 5, ¶4, e.g., obtain the first synchronization time and the second synchronization time through the software time stamp and the hardware time stamp, and uses the error of the two synchronization times to determine the time after the slave clock is synchronized with the master clock, so using the software time stamp to check the hardware time stamp so that the clock synchronization function satisfies the function security, using the software time stamp to perform the feature of the clock synchronization function is capable of satisfying the security requirement, using the hardware time stamp to perform the feature of the clock synchronization function is high in precision).
It would have been obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Gareau to incorporate the teachings of CHEN to include synchronization handshake execution at a software application layer. Doing so would facilitate in achieving the clock synchronization with high precision and meeting the safety and security requirement as suggested by CHEN (see Pg. 2, ¶5, e.g., the purpose of the present application is to provide a clock synchronization method anda clock synchronization device, the hardware timestamp is verified by means of the software timestamp, so that the clock synchronization function satisfies the function security, and the clock synchronization with high accuracy can be realized while satisfying the function security requirement).
Regarding claim 13, and 21, Gareau as combined with CHEN teaches the limitations of Claim 8 and 19.
Gareau further teaches, wherein the control block comprises a fifth portion indicating a fourth timestamp associated with transmitting the control block, wherein the device is further to:
determine a first difference between the fourth timestamp and the first timestamp; determine a second difference between the third timestamp and the second timestamp; and determine a delay associated with a first clock of the device by determining an average of the first difference and the second difference (see ¶ [0037], When the 66b block for timing transmitted by node B is detected at node A; node A samples time T.sub.A−A; the time T.sub.A−A is transferred to node B via a PTP message (step 108). With times T.sub.D−A, T.sub.A−B, T.sub.D−B, T.sub.A−A available at node B, the time delay between node A and node B is determined as: [00001]TIME_DELAY=R.Math.T.Math.D/2=[(TA-B-TD-A)+(TA-A-TD-B)]/2 ).
Regarding claim 14, Gareau as combined with CHEN teaches the limitations of Claim 13.
Gareau further teaches, wherein the device is to:
determine an offset associated with the first clock by determining a difference first timestamp, the fourth timestamp, and the delay (see ¶ [0038] Where RTD is the Round Trip Delay, which is [(T.sub.A−B−T.sub.D−A)+(T.sub.A−A−T.sub.D−B)]. The time error at node B is calculated as: TIME_ERROR=T.sub.A−B−(T.sub.D−A+TIME_DELAY) (step 110)).
Regarding claim 15, and 22, Gareau as combined with CHEN teaches the limitations of Claim 6 and 16.
Gareau does not teach but CHEN teaches, wherein the device is further to:
convert, at a driver of the device, the control block into a response having a first format different than a second format associated with the control block; and
transmit, via the driver, the response to an application layer of the device responsive to converting the control block into the response having the first format (see Pg. 6, ¶7, e.g., It can be understood that the clock synchronization signal should be any signal, and the purpose of the clock synchronization signal is to trigger and record the software and hardware time stamp in the signal transmission process at the Time master and Timeslaver terminals, so the signal format and content of the clock synchronization signal can be set arbitrarily. Pg. 6, ¶8, e.g., the signal transmission should be understood as any communication format suitable for automobile products, and the signal transmission channel at least comprises one of the following: vehicle Ethernet, CAN bus, CAN FD, FLEXRAY, SPI, UART.).
It would have been obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Gareau to incorporate the teachings of CHEN to include synchronization handshake execution at a software application layer. Doing so would facilitate in achieving the clock synchronization with high precision and meeting the safety and security requirement as suggested by CHEN (see Pg. 2, ¶5, e.g., the purpose of the present application is to provide a clock synchronization method and a clock synchronization device, the hardware timestamp is verified by means of the software timestamp, so that the clock synchronization function satisfies the function security, and the clock synchronization with high accuracy can be realized while satisfying the function security requirement).
Regarding claim 23, Gareau as combined with CHEN teaches the limitations of Claim 16.
Gareau does not teach but CHEN teaches, further comprising: transmitting the first timestamp to an application layer of the device (see Pg. 2, ¶7, e.g., when receiving the clock synchronous signal sent by the main clock, respectively recording the first hardware time stamp and the first software time stamp through the hardware layer and the software layer of the signal transmission channel of the secondary clock;).
It would have been obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Gareau to incorporate the teachings of CHEN to include synchronization handshake execution at a software application layer. Doing so would facilitate in achieving the clock synchronization with high precision and meeting the safety and security requirement as suggested by CHEN (see Pg. 2, ¶5, e.g., the purpose of the present application is to provide a clock synchronization method and a clock synchronization device, the hardware timestamp is verified by means of the software timestamp, so that the clock synchronization function satisfies the function security, and the clock synchronization with high accuracy can be realized while satisfying the function security requirement).
Claim(s) 5, is rejected under 35 U.S.C. 103 as being Unpatentable over Gareau combined with CHEN and in further view of AGARWAL et al., US 20240163000 A1, (hereinafter AGARWAL).
Regarding claim 5, Gareau as combined with CHEN teaches the limitations of Claim 1.
Gareau combined with CHEN does not teach but AGARWAL teaches, wherein the first control block further comprises a time portion of bits corresponding to a time of day (TOD) (see ¶ [0096], the time synchronization information 216 may include or represent a clock value (e.g., a time of day) of the clock 220 of the leader device 214.).
It would have been obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified control block of Gareau to incorporate the teachings of AGARWAL to include time of day (TOD). Doing so would facilitate in achieving the clock synchronization with using any suitable format for the clock value as suggested by AGARWAL (see ¶ [0034], e.g., The term “clock value” may be used in the present disclosure to describe a value of the time of day of a clock. Illustratively, a “clock value” may be or represent the (actual) time of day as indicated by the clock. A “clock value” may be represented in any suitable format, e.g. for processing by a device (e.g., for processing by a circuit)).
Claim(s) 11, is rejected under 35 U.S.C. 103 as being Unpatentable over Gareau combined with CHEN and in further view of Chen et al., CN 106850116 A (see the English Translated copy), (hereinafter Chen).
Regarding claim 11, Gareau as combined with CHEN teaches the limitations of Claim 10.
Gareau as combined with CHEN does not teach but Chen teaches, wherein executing the synchronization handshake comprises setting a time, adjusting a time, adjusting a phase, or adjusting a frequency (see Pg. 3, ¶4, e.g., adjusting the local clock S4, the non-root nodes S3 to obtain the clock drift and clock offset b, after synchronization with the root node).
It would have been obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified clock synchronization of Gareau and CHEN to incorporate the teachings of Chen to include adjusting a time on synchronization handshake execution. Doing so would facilitate in achieving synchronization with high precision as suggested by Chen (see ¶ [0034], e.g., The purpose of the invention is to provide a flooding time linear weighted least-squares-based synchronization method, the flooding time synchronous linear regression method algorithm is improved, eliminating the synchronization precision of observation noise. searching for a node the time of observation noise by linear weighted least-squares linear fitting, the time for obtaining the clock drift and clock offset at the same time, reducing the synchronous precision of observation noise, so as to realize synchronization with high precision).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to POONAM SHARMA whose telephone number is (571)272-6579. The examiner can normally be reached Monday thru 8:30-5:30 pm, ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kevin Bates can be reached at (571) 272-3980. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/POONAM SHARMA/Examiner, Art Unit 2472
/KEVIN T BATES/Supervisory Patent Examiner, Art Unit 2472