DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Claims 1–20 are presented for examination in a continuation application filed on 07/31/2023.
Drawings
3. The drawings were received on 07/31/2023 (in the filings). These drawings are acceptable.
Double Patenting
4. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
5. Claims 1–20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1–------20 of U.S. Patent No. 11,720,399 B2 (“’399 Patent”), since the claims, if allowed, would improperly extend the “right to exclude” already granted in the patent.
6. Although the claims at issue are not identical, they are not patentably distinct (nonobvious) from each other, because at least some of the subject matter claimed in the instant application is already fully disclosed in the copending applications.
For purposes of illustration, a table has been constructed below to compare the two independent method claims and exemplary dependent claims.
Instant Application No. 18/228,545
Issued ’399 Patent
1. A method of scheduling tasks within a processor, the tasks having task identifiers, wherein a task identifier is a task type identifier or a source identifier, the method comprising:
updating wakeup event state data of the processor to indicate a wakeup event for the task identifier of the task;
identifying one or more candidate task types or sources based on the wakeup event state data indicating a wakeup event; and
selecting a task for execution based on the identified one or more candidate task types or sources.
1. A method of scheduling tasks in a task queue within a processor, the task queue comprising tasks having task identifiers, wherein a task identifier is a task type identifier or a source identifier, the method comprising:
in response to receiving, at a task scheduling engine, an indication that a dependency for a task in the task queue has completed, updating wakeup event state data of the processor to indicate a wakeup event for the task identifier of the task;
identifying one or more candidate task types or sources based on the wakeup event state data indicating a wakeup event; and
selecting a task for execution based on the identified one or more candidate task types or sources.
2. The method according to claim 1, further comprising clearing a state bit for the task.
2. The method according to claim 1, further comprising, in response to receiving an indication that a dependency for a task in the task queue has completed, clearing a state bit for the task that relates to the completed dependency.
…
…
9. The method according to claim 1, further comprising:
in response to receiving, at the task scheduling engine, an indication that a task has completed execution, determining if the task is a first phase task of a multi-phase task; and
in response to determining that the task is a first phase task of a multi-phase task, scheduling a second phase task of the multi-phase task.
9. The method according to claim 1, further comprising:
in response to receiving, at the task scheduling engine, an indication that a task has completed execution, determining if the task is a first phase task of a multi-phase task;
in response to determining that the task is not a first phase task of a multi-phase task, removing the task from the task queue; and
in response to determining that the task is a first phase task of a multi-phase task, scheduling a second phase task of the multi-phase task.
…
…
20. An integrated circuit manufacturing system comprising:
a non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that describes a scheduler;
a layout processing system configured to process the integrated circuit description so as to generate a circuit layout description of an integrated circuit embodying the scheduler; and
an integrated circuit generation system configured to manufacture the scheduler according to the circuit layout description …
20. An integrated circuit manufacturing system comprising:
a non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that describes a scheduler;
a layout processing system configured to process the integrated circuit description so as to generate a circuit layout description of an integrated circuit embodying the scheduler; and
an integrated circuit generation system configured to manufacture the scheduler according to the circuit layout description …
7. Claims 1–20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1–------20 of U.S. Patent No. 11,204,800 B2 (“’800 Patent”), since the claims, if allowed, would improperly extend the “right to exclude” already granted in the patent.
8. Although the claims at issue are not identical, they are not patentably distinct (nonobvious) from each other, because at least some of the subject matter claimed in the instant application is already fully disclosed in the copending applications.
For purposes of illustration, a table has been constructed below to compare the two independent method claims and exemplary dependent claims.
Instant Application No. 18/228,545
Issued ’800 Patent
1. A method of scheduling tasks within a processor, the tasks having task identifiers, wherein a task identifier is a task type identifier or a source identifier, the method comprising:
updating wakeup event state data of the processor to indicate a wakeup event for the task identifier of the task;
identifying one or more candidate task types or sources based on the wakeup event state data indicating a wakeup event; and
selecting a task for execution based on the identified one or more candidate task types or sources.
1. A method of scheduling tasks in a task queue within a processor, the task queue comprising tasks having source identifiers and associated state data identifying any task specific dependencies, the method comprising:
in response to receiving, at a task scheduling engine, an indication that a dependency for a task in the task queue has completed, updating the state data for the task that relates to the completed dependency to indicate that the dependency has completed and updating wakeup event state data of the processor to indicate a wakeup event for the source identifier of the task;
identifying one or more candidate sources based on the wakeup event state data indicating a wakeup event; and
selecting a task for execution based on the identified one or more candidate sources.
2. The method according to claim 1, further comprising clearing a state bit for the task.
3. The method according to claim 1, wherein updating state data for the task that relates to the completed dependency comprises clearing a state bit for the task that relates to the completed dependency.
…
…
9. The method according to claim 1, further comprising:
in response to receiving, at the task scheduling engine, an indication that a task has completed execution, determining if the task is a first phase task of a multi-phase task; and
in response to determining that the task is a first phase task of a multi-phase task, scheduling a second phase task of the multi-phase task.
10. The method according to claim 1, further comprising:
in response to receiving, at the task scheduling engine, an indication that a task has completed execution, determining if the task is a first phase task of a multi-phase task;
in response to determining that the task is not a first phase task of a multi-phase task, removing the task from the task queue; and
in response to determining that the task is a first phase task of a multi-phase task, scheduling a second phase task of the multi-phase task.
…
…
20. An integrated circuit manufacturing system comprising:
a non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that describes a scheduler;
a layout processing system configured to process the integrated circuit description so as to generate a circuit layout description of an integrated circuit embodying the scheduler; and
an integrated circuit generation system configured to manufacture the scheduler according to the circuit layout description …
20. An integrated circuit manufacturing system comprising:
a non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that describes a scheduler;
a layout processing system configured to process the integrated circuit description so as to generate a circuit layout description of an integrated circuit embodying the scheduler; and
an integrated circuit generation system configured to manufacture the scheduler according to the circuit layout description …
9. Claims 1–20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1–------20 of U.S. Patent No. 10,503,547 B2 (“’547 Patent”), since the claims, if allowed, would improperly extend the “right to exclude” already granted in the patent.
10. Although the claims at issue are not identical, they are not patentably distinct (nonobvious) from each other, because at least some of the subject matter claimed in the instant application is already fully disclosed in the copending applications.
For purposes of illustration, a table has been constructed below to compare the two independent method claims.
Instant Application No. 18/228,545
Issued ’547 Patent
1. A method of scheduling tasks within a processor, the tasks having task identifiers, wherein a task identifier is a task type identifier or a source identifier, the method comprising:
updating wakeup event state data of the processor to indicate a wakeup event for the task identifier of the task;
identifying one or more candidate task types or sources based on the wakeup event state data indicating a wakeup event; and
selecting a task for execution based on the identified one or more candidate task types or sources.
1. A method of scheduling tasks in a task queue within a processor, the task queue comprising tasks having task type identifiers and associated state data identifying any task specific dependencies, the method comprising:
in response to receiving, at a task scheduling engine, an indication that a dependency for a task in the task queue has completed, updating the state data for the task that relates to the completed dependency to indicate that the dependency has completed and updating wakeup event state data of the processor to indicate a wakeup event for the task type identifier of the task;
identifying one or more candidate task types based on the wakeup event state data indicating a wakeup event; and
selecting a task for execution based on the identified one or more candidate task types.
11. Claims 1–20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1–------20 of U.S. Patent No. 10,318,348 B2 (“’348 Patent”), since the claims, if allowed, would improperly extend the “right to exclude” already granted in the patent.
12. Although the claims at issue are not identical, they are not patentably distinct (nonobvious) from each other, because at least some of the subject matter claimed in the instant application is already fully disclosed in the copending applications.
For purposes of illustration, a table has been constructed below to compare the two independent method claims.
Instant Application No. 18/228,545
Issued ’348 Patent
1. A method of scheduling tasks within a processor, the tasks having task identifiers, wherein a task identifier is a task type identifier or a source identifier, the method comprising:
updating wakeup event state data of the processor to indicate a wakeup event for the task identifier of the task;
identifying one or more candidate task types or sources based on the wakeup event state data indicating a wakeup event; and
selecting a task for execution based on the identified one or more candidate task types or sources.
1. A method of scheduling tasks in a task queue within a processor, the task queue comprising tasks having task type identifiers and associated state data identifying any task specific dependencies, the method comprising:
in response to receiving, at a task scheduling engine, an indication that a dependency for a task in the task queue has completed, updating the state data for the task that relates to the completed dependency to indicate that the dependency has completed and updating wakeup event state data of the processor to indicate a wakeup event for the task type identifier of the task;
identifying one or more candidate task types based on the wakeup event state data indicating a wakeup event;
selecting one of the candidate task types;
identifying an oldest non-executing task of the selected task type in the task queue; and
in response to determining that the identified task of the selected task type has all its dependencies met, selecting the task for execution.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
13. Claims 7–10 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
a. Specifically, the following term(s) and/or phrase(s) in the claim language is/are indefinite.
i. As to claims 7–10, the term “the task scheduling engine” lacks explicitly antecedent basis which renders the claims indefinite.
To proceed in examination, this element is interpreted as the element (i.e. processor) performing the task scheduling of claim 1.
b. Appropriate corrections are therefore required.
Examiner’s Remarks
14. Examiner refers to and explicitly cites particular pages, sections, figures, paragraphs or columns and lines in the references as applied to Applicant’s claims to the extent practicable to streamline prosecution.
Although the cited portions of the references are representative of the best teachings in the art and are applied to meet the specific limitations of the claims, other uncited but related teachings of the references may be equally applicable as well. It is respectfully requested that, in preparing responses to the rejections, the Applicant fully considers not only the cited portions of the references, but also the references in their entirety, as potentially teaching, suggesting or rendering obvious all or one or more aspects of the claimed invention.
Abbreviations
15. Where appropriate, the following abbreviations will be used when referencing Applicant’s submissions and specific teachings of the reference(s):
i. figure / figures: Fig. / Figs.
ii. column / columns: Col. / Cols.
iii. page / pages: p. / pp.
References Cited
16. (A) Browning et al., US 6,006,247 (“Browning”).
(B) Kang et al., US 7,904,703 B1 (“Kang”).
(C) Willen et al., US 2004/0054999 A1 (“Willen”).
(D) Verne et al., US 9,405,602 B1 (“Verne”).
(E) Arguelles, US 9,459,980 B1 (“Arguelles”).
(F) Haas et al., 2011/0292056 A1 (“Haas”).
(G) Webber et al., US 10,372,453 B2 (“Webber”).
Notice re prior art available under both pre-AIA and AIA
17. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A.
18. Claims 1–3 and 11–13 are rejected under 35 U.S.C. 103 as being unpatentable over (A) Browning in view of (B) Kang.
See “References Cited” section, above, for full citations of references.
19. Regarding claim 1, (A) Browning teaches/suggests the invention substantially as claimed, including:
“A method of scheduling tasks within a processor, the tasks having task identifiers, wherein a task identifier is a task type identifier or a source identifier, the method comprising:
(Col. 6, lines 57–65: process records the identifier of the current thread within a sleep list maintained in global memory 36. The sleep list simply lists all threads within 60 system unit 12 which are in state TSSLEEP;
Fig. 9 and Col. 8, lines 31–36: recording the THREAD IDENTIFIER in the sleep list maintained in global memory 36. The wait type of the thread to be put to sleep is then set at block 224 to specify which event will wake up the requesting thread;
Fig. 10 and Col. 8, lines 44–58: wake up threads from the sleep list …. The occurrence of the event generates an interrupt which is processed according to the method illustrated in FIG. 10 by any processor 30 within system unit 12. The process proceeds from block 240 to block 242, which depicts processor 30 identifying which thread or threads on the sleep list within global memory 36 to wake up by comparing the event with the wait types associated with the threads in the sleep list. Once a thread has been identified at block 242, the process places the selected thread(s) on global execution queue 40
Col. 5, lines 27–30: execution of the thread requires a page of virtual memory not resident within global memory 38, execution of the thread must be suspended until the required page is loaded from secondary storage, teaching threads uses and processes data or pages;
See Kang, infra, Col. 9, lines 1–5: THREAD MAY PERFORM A CERTAIN TASK before handing off responsibility to another);
identifying one or more candidate task types or sources …; and
(Fig. 10 and Col. 8, lines 44–58: wake up threads from the sleep list …. identifying which thread or threads on the sleep list within global memory 36 to wake up by comparing the event with the wait types associated with the threads in the sleep list. Once a thread has been identified at block 242, the process places the selected thread(s) on global execution queue 40;
Col. 6, lines 48–52: processor 30 setting the wait type of the current 50 thread to specify the event which will “wake up” the current thread);
selecting a task for execution based on the identified one or more candidate task types or sources”
(Fig. 10 and Col. 8, lines 44–58: wake up threads from the sleep list …. identifying which thread or threads on the sleep list within global memory 36 to wake up by comparing the event with the wait types associated with the threads in the sleep list. Once a thread has been identified at block 242, the process places the selected thread(s) on global execution queue 40);
Browning does not teach “updating wakeup event state data of the processor to indicate a wakeup event for the task identifier of the task; identifying … based on the wakeup event state data indicating a wakeup event.”
(B) Kang, in the context of Browning’s teachings, however teaches or suggests implementing:
“updating wakeup event state data of the processor to indicate a wakeup event for the task identifier of the task; identifying … based on the wakeup event state data indicating a wakeup event”
(Col. 3, lines 17–25: multi thread processing device may include one or more registers associated with the first instruction execution thread and configured to store the bandwidth request mode. According to various ones of these embodiments, a register associated with a particular thread may include a control bit, which may be set and un-set to idle and wake the instruction execution thread;
Col. 8, lines 1–8: the control bit may also be modified to wake (un-idle) an idled instruction execution thread. In various embodiments, if scheduler 120 determines that an instruction execution thread is no longer in an idle mode, one or more execution cycles may then be allocated to the instruction execution thread).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of B) Kang with those of (A) Browning to implement a control register/bits to control the idling and waking of threads on the sleep list. The motivation or advantage to do so is to provide simple and direct control mechanism for idling and waking multiple threads.
20. Regarding claim 2, Kang teaches or suggests:
“clearing a state bit for the task”
(Col. 3, lines 17–25: a control bit, which may be set and un-set to idle and wake the instruction execution thread;
Col. 8, lines 1–8: the control bit may also be modified to wake (un-idle) an idled instruction execution thread).
21. Regarding claim 3, Browning and Kang in combination teach or suggest:
“wherein updating wakeup event state data for the task identifier of the task comprises setting a wakeup event state bit for a task type or source corresponding to the task identifier of the task”
(Browning — Fig. 10 and Col. 8, lines 44–58: wake up threads from the sleep list …. identifying which thread or threads on the sleep list within global memory 36 to wake up by comparing the event with the wait types associated with the threads in the sleep list. Once a thread has been identified at block 242, the process places the selected thread(s) on global execution queue 40;
Col. 6, lines 48–52: processor 30 setting the wait type of the current 50 thread to specify the event which will “wake up” the current thread);
Kang — Col. 3, lines 17–25: a control bit, which may be set and un-set to idle and wake the instruction execution thread;
Col. 8, lines 1–8: the control bit may also be modified to wake (un-idle) an idled instruction execution thread).
22. Regarding claim 11, it is the corresponding system claim reciting similar limitations of commensurate scope as the method of claim 1. Therefore, it is rejected on the same basis as claim 1, above, including the following rationale:
Browning and Kang teach or suggest implementing “a task scheduling engine for scheduling tasks”
“a data store arranged to store wakeup state data” and
“a first hardware logic block … a second hardware logic block”
(Browning, Fig. 2 and Col. 4, lines 5–10: System unit 12 includes a number of processors;
Col. 4, lines 20–22: global memory 36 may include one or more individual modules of physical memory;
Col. 1, lines 30–35: processor context includes not only an indication of which instruction within the thread to execute subsequent to handling the interrupt or exception, but also the value of data and status registers within the processor;
Kang, Fig. 3 and Col. 10, lines 1–8: computer-executable instructions may be written in a computer programming language or may be embodied in firmware logic. If written in a programming language conforming to a recognized standard, such instructions may be executed on a variety of hardware platforms and for interface to a variety of operating systems, such as multithread aware and non-multithread operating systems).
23. Regarding claim 12, Kang teaches or suggests:
“wherein the wakeup state data comprises a plurality of wakeup state bits”
(Col. 3, lines 17–25: multi thread processing device may include one or more registers associated with the first instruction execution thread and configured to store the bandwidth request mode. According to various ones of these embodiments, a register associated with a particular thread may include a control bit, which may be set and un-set to idle and wake the instruction execution thread;
Col. 8, lines 1–8: the control bit may also be modified to wake (un-idle) an idled instruction execution thread. In various embodiments, if scheduler 120 determines that an instruction execution thread is no longer in an idle mode, one or more execution cycles may then be allocated to the instruction execution thread).
24. Regarding claim 13, it is the corresponding system claim reciting similar limitations of commensurate scope as the method of claims 2 and 3 in combination. Therefore, it is rejected on the same basis as claims 2 and 3 above.
B.
25. Claims 4–5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over (A) Browning in view of (B) Kang, as applied to claims 1 and 13 above, and further in view of (C) Willen.
26. Regarding claim 4, Browning and Kang in combination teach or suggest:
“wherein a task has a … a task identifier …,
(Browning — Col. 6, lines 57–65: process records the identifier of the current thread within a sleep list maintained in global memory 36. The sleep list simply lists all threads within 60 system unit 12 which are in state TSSLEEP;
Fig. 9 and Col. 8, lines 31–36: recording the THREAD IDENTIFIER in the sleep list maintained in global memory 36. The wait type of the thread to be put to sleep is then set at block 224 to specify which event will wake up the requesting thread;
Fig. 10 and Col. 8, lines 44–58: wake up threads from the sleep list …. The occurrence of the event generates an interrupt which is processed according to the method illustrated in FIG. 10 by any processor 30 within system unit 12. The process proceeds from block 240 to block 242, which depicts processor 30 identifying which thread or threads on the sleep list within global memory 36 to wake up by comparing the event with the wait types associated with the threads in the sleep list. Once a thread has been identified at block 242, the process places the selected thread(s) on global execution queue 40);
wherein the wakeup event state data is updated for a combination of the task type or source corresponding to the task identifier of the task …,
(Browning — Fig. 10 and Col. 8, lines 44–58: wake up threads from the sleep list …. identifying which thread or threads on the sleep list within global memory 36 to wake up by comparing the event with the wait types associated with the threads in the sleep list. Once a thread has been identified at block 242, the process places the selected thread(s) on global execution queue 40;
Col. 6, lines 48–52: processor 30 setting the wait type of the current 50 thread to specify the event which will “wake up” the current thread;
Kang — Col. 3, lines 17–25: multi thread processing device may include one or more registers associated with the first instruction execution thread and configured to store the bandwidth request mode. According to various ones of these embodiments, a register associated with a particular thread may include a control bit, which may be set and un-set to idle and wake the instruction execution thread;
Col. 8, lines 1–8: the control bit may also be modified to wake (un-idle) an idled instruction execution thread. In various embodiments, if scheduler 120 determines that an instruction execution thread is no longer in an idle mode, one or more execution cycles may then be allocated to the instruction execution thread).
and wherein selecting a task for execution based on the identified one or more candidate task types or sources comprises:
selecting a task for execution based on the identified one or more candidate task types or sources that has a task identifier … that correspond to wakeup event state data that has been updated”
(Browning — Fig. 10 and Col. 8, lines 44–58: wake up threads from the sleep list …. identifying which thread or threads on the sleep list within global memory 36 to wake up by comparing the event with the wait types associated with the threads in the sleep list. Once a thread has been identified at block 242, the process places the selected thread(s) on global execution queue 40;
Col. 6, lines 48–52: processor 30 setting the wait type of the current 50 thread to specify the event which will “wake up” the current thread);
Kang — Col. 3, lines 17–25: a control bit, which may be set and un-set to idle and wake the instruction execution thread;
Col. 8, lines 1–8: the control bit may also be modified to wake (un-idle) an idled instruction execution thread).
Browning and Kang do not teach “wherein a task has … a data group identifier; wherein the wakeup event state data is updated … corresponding to the task identifier of the task and the data group corresponding to the data group identifier of the task.”
(C) Willen, in the context of Browning and Kang’s teachings, however teaches or suggests implementing:
“wherein a task has … a data group identifier; wherein the wakeup event state data is updated … corresponding to the task identifier of the task and the data group corresponding to the data group identifier of the task.”
(¶ 61: to declare certain important tasks to be a data-sharing group whether they constitute an “application” or not. These data-sharing groups can be dynamically redefined whenever the user wants to change the application mix or the relative importance of applications;
¶ 62: a DATA-SHARING GROUP comprises a list of tasks, and includes all the related threads of control. This can be enhanced so that a data-sharing group could comprise all the transactions that update a particular database or segment thereof. For example, it could include all the reservation transactions and queries for an airline. It could also be applied to the OS itself, such that, for example, a data-sharing group could include all the OS tasks involved in network message handling;
¶ 63: employing a “RUNID” or “TASK.ID” that a user uses to identify these tasks, transactions, threads, and the like with a dedicated data-sharing group;
Claim 9: a structure for each set of applications related within a Data Sharing Group having a Data Sharing Group ID with each task sharing said Data Sharing Group ID being a member within a Data Sharing Group ID membership list).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of (C) Willen with those of (A) Browning and (B) Kang to idle and wake a group of tasks based on a data sharing group identifier. The motivation or advantage to do so is to control the idling and waking of a group of related, application- or transaction-specific tasks (accessing or managing same data set).
27. Regarding claim 5, Browning, Kang, and Willen in combination teach or suggest:
“wherein a wakeup event state bit is set for the combination of the task type or source corresponding to the task identifier of the task and the data group corresponding to the data group identifier of the task and selecting a task for execution based on the identified one or more candidate task types or sources that has a task identifier and data group identifier that correspond to wakeup event state data that has been updated comprises:
selecting a task for execution based on the identified one or more candidate task types or sources that has a task identifier and data group identifier that correspond to a wakeup event state bit that has been set”
(Browning — Fig. 10 and Col. 8, lines 44–58: wake up threads from the sleep list …. identifying which thread or threads on the sleep list within global memory 36 to wake up by comparing the event with the wait types associated with the threads in the sleep list. Once a thread has been identified at block 242, the process places the selected thread(s) on global execution queue 40;
Col. 6, lines 48–52: processor 30 setting the wait type of the current 50 thread to specify the event which will “wake up” the current thread);
Kang — Col. 3, lines 17–25: a control bit, which may be set and un-set to idle and wake the instruction execution thread;
Col. 8, lines 1–8: the control bit may also be modified to wake (un-idle) an idled instruction execution thread).
Kang — ¶ 61 to ¶ 63, as applied in rejecting claim 4 above;
Claim 9: a structure for each set of applications related within a Data Sharing Group having a Data Sharing Group ID with each task sharing said Data Sharing Group ID being a member within a Data Sharing Group ID membership list).
28. Regarding claim 14, it is the corresponding system claim reciting similar limitations of commensurate scope as the method of claim 4. Therefore, it is rejected on the same basis as claim 4 above.
C.
29. Claims 7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over (A) Browning in view of (B) Kang, as applied to claims 1 and 11 above, and further in view of (D) Verne.
30. Regarding claim 7, Browning teaches “task scheduling engine, adding the task to a task queue”
(Col. 4, lines 27–30: processor 30 runs a dispatcher routine which selects a thread from global execution 40 for execution by processor;
Col. 7, lines 12–15: global dispatch flag 48 is incremented to indicate that a thread has been added to global execution queue).
Browning and Kang do not teach but —
(D) Verne, in the context of Browning and Kang’s teachings, however teaches or suggests implementing:
“in response to receiving a task at the task scheduling engine, adding the task to a task queue”
(Col. 3, lines 9–15: append the task to the task queue; and assign the task to a worker process in the internal application such that the worker process leases the task from the task queue, processes the task, and responsive to completing the task, removes the task from the task queue;
Col. 3, lines 40–42: task, inserting a task into the task queue, deleting a task from the task queue, updating a task in the task queue;
Fig. 3 and Col. 5, lines 42–47: receiving a task from an external application (302). If the external application is in the ACL list of an internal application’s queue configuration file and the application has the appropriate privilege, the task will be appended to the task queue associated with the internal application).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of (D) Verne with those of (A) Browning and (B) Kang to add (insert, append) received application tasks to a task queue of a processor. The motivation or advantage to do so is to manage the ordering and execution of application tasks.
31. Regarding claim 16, it is the corresponding system claim reciting similar limitations of commensurate scope as the method of claim 7. Therefore, it is rejected on the same basis as claim 7 above.
D.
32. Claims 8 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over (A) Browning in view of (B) Kang, as applied to claims 1 and 11 above, and further in view of (E) Arguelles.
33. Regarding claim 8, Browning teaches “task scheduling engine … a task queue”
(Col. 4, lines 27–30: processor 30 runs a dispatcher routine which selects a thread from global execution 40 for execution by processor;
Col. 7, lines 12–15: global dispatch flag 48 is incremented to indicate that a thread has been added to global execution queue).
Browning and Kang do not teach but —
(E) Arguelles, in the context of Browning and Kang’s teachings, however teaches or suggests implementing:
“in response to receiving, at the task scheduling engine, an indication that a task has completed execution, removing the task from a task queue”
(Fig. 17 and Col. 27, line 37 to Col. 28, line 5: 1700, a worker accesses a job queue ( e.g., job queue 550 in FIG. 5) to find a job. For example, jobs may be ordered by age in the job queue. When a worker access the job queue for a job, the oldest available (e.g., untaken) job may be indicated to the worker …. once the job completes, notification may be sent by the worker (e.g., worker 530 in FIG. 5) to the queue ( e.g., queue 550 in FIG. 5) indicating that the job (e.g., job 540) can be deleted from the queue, as indicated in 1780. The worker that processed the completed job can access the next untaken job in the job queue ( e.g., return to 1700)).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of (E) Arguelles with those of (A) Browning and (B) Kang to remove application tasks from a task queue of a processor. The motivation or advantage to do so is to manage/control the ordering and execution of application tasks.
34. Regarding claim 17, it is the corresponding system claim reciting similar limitations of commensurate scope as the method of claim 8. Therefore, it is rejected on the same basis as claim 8 above.
E.
35. Claims 9–10 and 18–19 are rejected under 35 U.S.C. 103 as being unpatentable over (A) Browning in view of (B) Kang, as applied to claims 1 and 11 above, and further in view of (E) Arguelles and (F) Haas.
36. Regarding claim 9, Browning teaches “task scheduling engine … a task queue”
(Col. 4, lines 27–30: processor 30 runs a dispatcher routine which selects a thread from global execution 40 for execution by processor;
Col. 7, lines 12–15: global dispatch flag 48 is incremented to indicate that a thread has been added to global execution queue).
Browning and Kang do not teach but —
(E) Arguelles, in the context of Browning and Kang’s teachings, however teaches or suggests implementing:
“in response to receiving, at the task scheduling engine, an indication that a task has completed execution ….”
(Fig. 17 and Col. 27, line 37 to Col. 28, line 5: 1700, a worker accesses a job queue ( e.g., job queue 550 in FIG. 5) to find a job. For example, jobs may be ordered by age in the job queue. When a worker access the job queue for a job, the oldest available (e.g., untaken) job may be indicated to the worker …. once the job completes, notification may be sent by the worker (e.g., worker 530 in FIG. 5) to the queue ( e.g., queue 550 in FIG. 5) indicating that the job (e.g., job 540) can be deleted from the queue, as indicated in 1780. The worker that processed the completed job can access the next untaken job in the job queue ( e.g., return to 1700)).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of (E) Arguelles with those of (A) Browning and (B) Kang to remove application tasks from a task queue of a processor. The motivation or advantage to do so is to manage/control the ordering and execution of application tasks.
Browning, Kang, and Arguelles do not teach “determining if the task is a first phase task of a multi-phase task; and in response to determining that the task is a first phase task of a multi-phase task, scheduling a second phase task of the multi-phase task.”
(F) Haas, in the context of Browning, Kang, and Arguelles’s teachings, however teaches or suggests implementing:
“determining if the task is a first phase task of a multi-phase task; and in response to determining that the task is a first phase task of a multi-phase task, scheduling a second phase task of the multi-phase task”
(Fig. 5 and ¶ 46: schedule 500 may be implemented as a plurality of tasks distributed in parallel over a plurality of phases. The schedule 500 may be generated as the schedule 307 from the computing environment 300 described above with respect to FIG. 3. FIG. 5 depicts an exemplary optimal sequence of tasks for generating a desired output derived from the dependency network;
¶ 47: As presented in FIG. 5, Task 1, which is dependent on the output of Task 5 and Task 3, is performed during the last phase (Phase 3 505). Task 5 and Task 3, which both require the output of Task 4, are distributed in Phase 2 503;
¶ 48: Accordingly, multi-phase schedules with multiple processing threads provide the ability to leverage advanced computing resources by optimally utilizing multiple processors for efficiently generating variable and customizable automatically created schedules).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of (F) Haas with those of (A) Browning, (B) Kang, and (E) Arguelles to implement multi-phase task scheduling (and dispatching). The motivation or advantage to do so is to generate an efficient parallel schedule of dependent tasks.
37. Regarding claim 10, Browning and Arguelles, in combination, teach or suggest:
“selecting a task for execution based on the identified one or more candidate task types or sources further comprises prioritizing selection of a task that is a second phase task of a
multi-phase task over tasks that are not second phase tasks”
(Browning — Fig. 10 and Col. 8, lines 44–58: wake up threads from the sleep list …. identifying which thread or threads on the sleep list within global memory 36 to wake up by comparing the event with the wait types associated with the threads in the sleep list. Once a thread has been identified at block 242, the process places the selected thread(s) on global execution queue 40;
Col. 6, lines 48–52: processor 30 setting the wait type of the current 50 thread to specify the event which will “wake up” the current thread;
Col. 7, lines 64–66: determining which thread within global execution queue 40 has the highest priority and removing the selected thread from global execution queue 40;
Arguelles — Fig. 5 and ¶ 46: schedule 500 may be implemented as a plurality of tasks distributed in parallel over a plurality of phases. The schedule 500 may be generated as the schedule 307 from the computing environment 300 described above with respect to FIG. 3. FIG. 5 depicts an exemplary optimal sequence of tasks for generating a desired output derived from the dependency network;
¶ 47: As presented in FIG. 5, Task 1, which is dependent on the output of Task 5 and Task 3, is performed during the last phase (Phase 3 505). Task 5 and Task 3, which both require the output of Task 4, are distributed in Phase 2 503;
¶ 48: Accordingly, multi-phase schedules with multiple processing threads provide the ability to leverage advanced computing resources by optimally utilizing multiple processors for efficiently generating variable and customizable automatically created schedules).
38. Regarding claims 18–19, they are the corresponding system claims reciting similar limitations of commensurate scope as the method of claims 9–10. Therefore, they are rejected on the same basis as claims 9–10 above.
F.
39. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over (A) Browning in view of (B) Kang and (G) Webber.
40. Regarding claim 20, Browning and Kang teach or suggest “the scheduler comprises:
a task scheduling engine for scheduling tasks, the tasks having task identifiers, wherein a task identifier is a task type identifier or a source identifier; and
a data store arranged to store wakeup state data;
wherein the task scheduling engine comprises: a first hardware logic block arranged to update wakeup event state data of the processor to indicate a wakeup event for the task identifier of the task; and
a second hardware logic block arranged to identify one or more candidate task types or sources based on the wakeup event state data indicating a wakeup event and to select a task for execution based on the identified one or more candidate task types or sources,” AS APPLIED IN REJECTING INDEPENDENT CLAIMS 1 AND 11 ABOVE
(further on the basis that it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of B) Kang with those of (A) Browning to implement a control register/bits to control the idling and waking of threads on the sleep list. The motivation or advantage to do so is to provide simple and direct control mechanism for idling and waking multiple threads).
Browning and Kang do not teach “An integrated circuit manufacturing system comprising:
a non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that describes a scheduler;
a layout processing system configured to process the integrated circuit description so as to generate a circuit layout description of an integrated circuit embodying the scheduler; and
an integrated circuit generation system configured to manufacture the scheduler according to the circuit layout description.”
(G) Webber however teaches or suggests:
“An integrated circuit manufacturing system comprising:
a non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that describes a scheduler;
a layout processing system configured to process the integrated circuit description so as to generate a circuit layout description of an integrated circuit embodying the scheduler; and
an integrated circuit generation system configured to manufacture the scheduler according to the circuit layout description”
(Col. 2, lines 35–45: There may be provided an INTEGRATED CIRCUIT MANUFACTURING SYSTEM comprising: a computer readable storage medium having stored thereon a computer readable integrated circuit description …
a layout processing system configured to process the integrated circuit description so as to generate a circuit layout description of an integrated circuit … and
an integrated circuit generation system configured to manufacture … according to the circuit layout description”
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of (G) Webber with those of (A) Browning and (B) Kang, to implementing an integrated manufacturing system to build the scheduler. The motivation or advantage to do so implement a standardized, automated production system/process for creating a hardware scheduler.
Allowable Subject Matter
41. Claims 6 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if 1) rewritten in independent form including all of the limitations of the base claim and any intervening claims, and 2) rewritten to overcome all applied rejections set forth in this action.
The following is the Examiner’s statement of reasons for allowance:
The prior art of record, when viewed individually or in combination, does not expressly teach nor render obvious the features of dependent claims 6 and 15 when viewed as a whole, specific to the limitation(s) of:
“in response to determining that the selected task does not have all its dependencies met, clearing the wakeup event state data for the task identifier and data group identifier of the identified task; and
selecting a task for execution based on the identified one or more candidate task types or sources that has a task identifier and data group identifier that correspond to wakeup event state data that has been updated.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
(a) Arimilli et al., US 8,312,458 B2, teaching wake-and-go mechanism with a central repository wake-and-go array for a multiple processor data processing system.
(b) Steffen et al., US 2014/0237476 A1, teaching registering and storing execution criteria for background task. The execution criteria indicates a criterion for launching the background task.
(c) Kamath et al., US 2012/0291034 A1, teaching receiving a wake-up signal for a thread and waiting for a global lock. In response receiving the global lock, the thread retrieves and processes a first message.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN C WU whose telephone number is (571)270-5906. The examiner can normally be reached Monday through Friday, 8:30 A.M. to 5:00 P.M..
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/BENJAMIN C WU/Primary Examiner, Art Unit 2195
April 16, 2026
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