CTNF 18/228,563 CTNF 87285 DETAILED ACTION This office action is in response to the amendment filed on 02/23/2026. Response to Arguments 07-38-02 Applicant’s arguments with respect to the rejection(s) of claim(s) 1-6 and 12-16 under Jaladanki in view of Wang have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Zhang. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1, 4, and 5 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Zhang et al. (“Zhang”, CN 111221369) . Re claim 1, Zhang teaches a circuit [Fig 2] comprising: an amplifier [OPA1] having a first input terminal [-], a second input terminal [+], and an output terminal; a transistor [M1] having a first current terminal, a second current terminal, and a control terminal, the control terminal of the transistor coupled to the output terminal of the amplifier [Fig 2]; and compensation circuitry [50] having a first terminal and a second terminal, the first terminal of the compensation circuitry coupled to the output terminal of the amplifier, the second terminal of the compensation circuitry coupled to the second input terminal of the amplifier [as shown in Fig 2]. Re claim 4, Zhang teaches wherein the first current terminal of the transistor is coupled to a supply voltage terminal [VDDA]. Re claim 5, Zhang teaches wherein the first input terminal of the amplifier is coupled to a reference voltage terminal [VREF at 11] . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 6, 12, 15 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Jaladanki et al. (“Jaladanki”, US 2022/0149792) . Re claim 6, Zhang teaches wherein the compensation circuitry includes: a capacitor [C2] having a first terminal and a second terminal, the second terminal of the capacitor coupled to the second input terminal of the amplifier [+], but does not teach a resistor having a first terminal and a second terminal, the first terminal of the resistor coupled to the output terminal of the amplifier and the control terminal of the transistor. Jaladanki teaches a device [Fig 1] having a resistor [118] having a first terminal and a second terminal, the first terminal of the resistor coupled to the output terminal of the amplifier and the control terminal of the transistor. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Zhang to include the features of Jaladanki because it is known for compensation circuits to include a series connection of a resistor and capacitor, thus improving the quality of the device, which increases efficiency. Re claim 12, Zhang teaches a voltage regulator [Fig 2] comprising: an amplifier [OPA1] having a first input terminal [-], a second input terminal [+], and an output terminal [output of OPA1]; a transistor [M1] having a first terminal, a second terminal, and a control terminal, and the control terminal of the transistor coupled to the output terminal of the amplifier [Fig 2]; the second terminal of the transistor structured to be coupled to the second input terminal of the amplifier [via M2]; and a capacitor [C2] having a first terminal and a second terminal, and the second terminal of the capacitor coupled to the second input terminal of the amplifier [+], but does not teach a resistor having a first terminal and a second terminal, the first terminal of the resistor coupled to the output terminal of the amplifier. Jaladanki teaches a device [Fig 1] having a resistor [118] having a first terminal and a second terminal, the first terminal of the resistor coupled to the output terminal of the amplifier. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Zhang to include the features of Jaladanki because it is known for compensation circuits to include a series connection of a resistor and capacitor, thus improving the quality of the device, which increases efficiency. Re claim 15, Zhang teaches wherein the first terminal of the transistor coupled to a supply voltage terminal [126]. Re claim 16, Zhang teaches the limitations as applied to the claim above but does not teach wherein the first input terminal of the amplifier is coupled to a reference voltage terminal . Allowable Subject Matter 12-151-07 AIA 07-97 12-51-07 Claim s 21-25 are allowed. 07-43-02 AIA Claim s 2, 3, 7-11, 13, 14, and 17-20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: the prior art fails to teach or disclose: Re claim 2 and its dependents thereof, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “the second terminal of the resistor coupled to the second terminal of the compensation circuitry and the second input terminal of the amplifier” in combination with the additionally claimed features, as are claimed by Applicant. Re claim 7 and its dependents thereof, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “a second capacitor having a first terminal and a second terminal, the first terminal of the second capacitor coupled to the second terminal of the resistor, the second terminal of the second capacitor coupled to the second terminal of the first resistor and the first terminal of the first capacitor” in combination with the additionally claimed features, as are claimed by Applicant. Re claim 9 and its dependents thereof, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “a second capacitor having a first terminal and a second terminal, the first terminal of the second capacitor structured to be coupled to the second terminal of the transistor via the third terminal of the compensation circuitry, the second terminal of the second capacitor coupled to the second input terminal of the amplifier and the second terminal of the first capacitor” in combination with the additionally claimed features, as are claimed by Applicant. Re claim 10 and its dependents thereof, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “current source circuitry having a first terminal and a second terminal, the first terminal of the current source circuitry coupled to a supply voltage terminal, the second terminal of the current source circuitry coupled to the first terminal of the transistor and the control terminal of the transistor” in combination with the additionally claimed features, as are claimed by Applicant. Re claim 13 and its dependents thereof, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “the second terminal of the second resistor coupled to the second terminal of the capacitor and the second input terminal of the amplifier” in combination with the additionally claimed features, as are claimed by Applicant. Re claim 17 and its dependents thereof, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “a second capacitor having a first terminal and a second terminal, the first terminal of the second capacitor coupled to the second terminal of the resistor, the second terminal of the second capacitor coupled to the second terminal of the first resistor and the first terminal of the first capacitor” in combination with the additionally claimed features, as are claimed by Applicant. Re claim 19 and its dependents thereof, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “current source circuitry having a first terminal and a second terminal, the first terminal of the current source circuitry coupled to a supply voltage terminal, the second terminal of the current source circuitry coupled to the first terminal of the transistor and the control terminal of the transistor” in combination with the additionally claimed features, as are claimed by Applicant. Re claim 20 and its dependents thereof, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “a second transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the second transistor coupled to the control terminal of the second transistor, and the second terminal of the second transistor coupled to the second terminal of the first transistor; and a second gain stage having a first input terminal, a second input terminal, and an output terminal, the first input terminal of the second gain stage coupled to the first terminal of the second transistor, and the second input terminal of the second gain stage coupled to the output terminal of the amplifier” in combination with the additionally claimed features, as are claimed by Applicant. Re claim 21 and its dependents thereof, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “ a second capacitor having a first terminal and a second terminal, the first terminal of the second capacitor structured to be coupled to the second terminal of the transistor, the second terminal of the second capacitor coupled to the second input terminal of the amplifier and the second terminal of the first capacitor” in combination with the additionally claimed features, as are claimed by Applicant. Re claim 25 and its dependents thereof, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “a second transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the second transistor coupled to the control terminal of the second transistor, and the second terminal of the second transistor coupled to the second terminal of the first transistor; a second amplifier having a first input terminal, a second input terminal, and an output terminal, the first input terminal of the second amplifier coupled to the first terminal of the second transistor, and the second input terminal of the second amplifier coupled to the output terminal of the first amplifier” in combination with the additionally claimed features, as are claimed by Applicant. Conclusion Examiner's Note: Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAKAISHA JACKSON whose telephone number is (571)270-3111. The examiner can normally be reached on M-F 8:00-5:00. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MONICA LEWIS can be reached on 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LaKaisha Jackson/ Examiner, Art Unit 2838 Application/Control Number: 18/228,563 Page 2 Art Unit: 2838 Application/Control Number: 18/228,563 Page 3 Art Unit: 2838 Application/Control Number: 18/228,563 Page 4 Art Unit: 2838 Application/Control Number: 18/228,563 Page 5 Art Unit: 2838 Application/Control Number: 18/228,563 Page 6 Art Unit: 2838 Application/Control Number: 18/228,563 Page 7 Art Unit: 2838 Application/Control Number: 18/228,563 Page 8 Art Unit: 2838 Application/Control Number: 18/228,563 Page 9 Art Unit: 2838 Application/Control Number: 18/228,563 Page 10 Art Unit: 2838
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