Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 – 7, 8 – 14 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the data processing measurement". There is insufficient antecedent basis for this limitation in the claim.
Regarding claim 8, the phrase “a hardware resource in a reduced power state device” is unclear. It is uncertain whether the claim requires a hardware resource that is itself in a reduced-power state or a hardware resource located within a device that is in a reduced-power state.
Regarding claims 4, 10, and 17, the recitation that “the data processing measurement is based on power up of” an interface and/or the hardware resource is unclear. The claims do not clearly identify whether the measurement represents the time or resources required to power up the interface or hardware resource, the processing performance after power-up, or a combination thereof. Accordingly, the scope of the claimed “data processing measurement” cannot be determined with reasonable certainty.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 - 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US Pub. N0. 20190004594), hereinafter referred to as Kim in view of Yao et al. (US Pub. No. 20230185624), hereinafter referred to as Yao.
As to claim 1, Kim discloses an apparatus comprising:
a network interface device comprising (enhanced NIC 302/500, Figs. 3A, 3B, and 5A, paras. 0034–0036 and 0044–0046):
direct memory access (DMA) circuitry (NIC DMA engine 302a transfers received packets into receive kernel buffers in main memory 304, Fig. 3B, para. 0036), a network interface (physical interface PHY 512 receives and transmits network packets, Fig. 5A, paras. 0046–0047), a host interface (PCIe connection between NIC 302/500 and processor PCIe Root Complex 308, Figs. 3A and 5A, paras. 0034 and 0046), an interface (PCIe 510 carries special interrupt 508 from enhanced NIC 500 to processor 306, Fig. 5A, paras. 0046–0047), and circuitry to (Decision Engine 502, ReqMonitor Counter 504, and TxBytes Counter 506 constitute NIC logic circuitry performing NCAP management, Fig. 5A, paras. 0045–0047): for a packet flow (received and transmitted latency-critical network packets monitored through ReqCnt 514 and TxCnt 516, Fig. 5A, paras. 0047 and 0051–0052), wherein the available hardware resources include a hardware resource in a reduced power state (processor cores may occupy idle, halt, sleep, or off C states having reduced power consumption, paras. 0029–0031), and based on receipt of a packet of the packet flow (enhanced NIC 302 examines a received network packet and detects latency-critical requests, Fig. 4, para. 0041) comprising data to process by a particular operation (packet payload identifies a requested operation such as GET, HEAD, POST, or PUT for processing by processor cores, Fig. 5B, paras. 0037 and 0049–0050), select a hardware resource in the reduced power state to process the data (Decision Engine 502 identifies a target processor core that is speculated to be in a C state and causes that core to transition to an active state to service the request, Figs. 5A and 5C, paras. 0048 and 0059).
Yao discloses, what Kim lacks, determine available hardware resources (Yao’s framework identifies available CPUs and accelerator processing units and develops a mapping between workload parameters and computing units capable of executing the workload, Fig. 1, paras. 0015–0016, 0021, and 0033) and based on the data processing measurement (Yao selects a particular computing unit from multiple available computing units based on a comparison of their respective performance metrics, including the time required to transfer the workload data to each computing unit, and selects the computing unit determined, based on those performance metrics, to execute the workload most efficiently, Fig. 1, paras. 0015–0016).
Kim and Yao are analogous art because they are from the same field of endeavor of selecting and managing hardware resources for processing network-packet workloads.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Kim and Yao before him or her, to modify the NCAP resource-management circuitry of Kim to include Yao’s performance-based resource-selection framework.
The suggestion and motivation for doing so would have been to select the available processing resource capable of efficiently completing the packet-requested operation while reducing processing delay.
Therefore, it would have been obvious to combine Yao with Kim to obtain the invention as specified in the instant claim.
As to claim 2, the modified system of Kim discloses the apparatus of claim 1, wherein the data processing measurement comprises one or more of (Kim’s speculated completion time and Yao’s comparative performance metrics, Kim, Figs. 4 and 5A, paras. 0041 and 0052; Yao, Fig. 1, paras. 0015–0016): time (Kim’s speculated time for processor 306 to complete services requested in latency-critical packets, Fig. 4, para. 0041) or number of clock cycles to process data or priority level of hardware resource to process the data.
As to claim 3, the modified system of Kim discloses the apparatus of claim 1, wherein the network interface device includes at least one hardware resource of the available hardware resources (Yao’s NIC/IPU includes programmable or fixed-function processors capable of performing operations offloaded from a CPU, Fig. 3, paras. 0064–0067), a host system includes at least one hardware resource of the available hardware resources (Yao’s available computing units include host CPUs and accelerator processing units for executing packet-associated workloads, Fig. 1, paras. 0015–0016 and 0032–0033), and the at least one hardware resource of the available hardware resources of the network interface device and the at least one hardware resource of the available hardware resources of the host system are in different packages (Yao discloses that a computing unit may be embodied as a discrete chip and that the NIC/IPU may be coupled to one or more servers, para. 0023 and Fig. 3, para. 0064).
As to claim 4, the modified system of Kim discloses the apparatus of claim 1, wherein the data processing measurement (Kim’s speculated completion time for processor 306 to handle each latency-critical request, Figs. 4 and 5A, paras. 0041 and 0052) is based on power up of the interface (Kim discloses communication between enhanced NIC 500 and processor 306 through PCIe 510, Fig. 5A, paras. 0046–0047) and the hardware resource in the reduced power state (Kim discloses wake-up latency associated with transitioning a processor core from a reduced-power C state, paras. 0029–0031 and 0037–0039) to operate at a first level of processing (Kim’s Decision Engine 502 causes necessary processor cores to transition from a low-performance or sleep state to the P0 highest-performance state, Fig. 5A, paras. 0047–0048).
As to claim 5, the modified system of Kim discloses the apparatus of claim 4, wherein the first level of processing comprises a data processing rate (Kim’s P0 highest-performance state defined by the highest operational voltage-and-frequency point, paras. 0025 and 0038) associated with a power consumption level (Kim’s processor-performance states are defined by operational voltage and frequency, with lower voltage or frequency decreasing power consumption, para. 0025) that is higher than a power consumption level of the reduced power state (Kim’s C states comprise idle, halt, sleep, and off states having reduced power consumption, and NCAP transitions the processor to P0 and increases its operational frequency to the maximum, paras. 0029, 0047, and 0057).
As to claim 6, the modified system of Kim discloses the apparatus of claim 1, wherein the interface is consistent with a Compute Express Link (CXL) protocol (Yao’s input/output interface 104 and NIC/IPU bus interface are expressly compatible with Compute Express Link, Figs. 1 and 3, paras. 0032, 0064, and 0075).
As to claim 7, the modified system of Kim discloses the apparatus of claim 1, wherein the select a hardware resource in the reduced power state to process the data based on the data processing measurement (Yao selects a particular computing unit from multiple available computing units based on a comparison of their respective performance metrics and selects the computing unit determined, based on those metrics, to execute the workload most efficiently, Fig. 1, paras. 0015–0016) is to prioritize use of a hardware resource in the network interface device (Yao discloses that the resource-selection framework may be implemented in a NIC/IPU containing programmable processors and that the NIC’s packet allocator distributes received packets among processing units, Fig. 3, paras. 0064 and 0067–0074).
As to claim 8, the modified system of Kim discloses a non-transitory computer-readable medium comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to: configure a network interface device to (Yao’s resource-selection framework may be implemented by processing circuitry of a NIC, network interface card, IPU, or DPU, Fig. 3, paras. 0064–0067): based on receipt of a packet with data to process by a particular operation (Yao’s interface 104 receives network packet 103 containing data associated with a workload such as encryption, decryption, compression, decompression, or machine learning, Fig. 1, paras. 0012, 0014, and 0032–0033): determine available hardware resources (Yao’s framework identifies available CPUs and accelerator processing units and develops a mapping between workload parameters and computing units capable of executing the workload, Fig. 1, paras. 0015–0016, 0021, and 0033), wherein the available hardware resources include a hardware resource in a reduced power state device (Kim’s available processor cores may occupy reduced-power C states including idle, halt, sleep, and off states, paras. 0029–0031) and select a hardware resource among the available hardware resources (Yao’s framework selects one computing unit from multiple available CPUs and accelerators to execute the packet-associated workload, Fig. 1, paras. 0015–0016 and 0033) based on a data processing measurement for the particular operation (Yao selects the computing unit based on comparative performance metrics, including data-transfer time and workload-execution efficiency, and selects the unit determined based on those measurements to execute the particular workload most efficiently, Fig. 1, paras. 0015–0016 and 0041).
The rationale for combining Kim and Yao regarding claim 8 is substantially the same as set forth above for claim 1.
As to claim 9, the modified system of Kim discloses the computer-readable medium of claim 8, wherein the data processing measurement for the particular operation comprise one or more of (Yao’s comparative performance metrics determine which available computing unit most efficiently executes the particular workload, Fig. 1, paras. 0015–0016 and 0041): time (Yao considers the time required to transfer workload data to a computing unit, Fig. 1, para. 0016) or number of clock cycles to process data or priority level of hardware resource to process the data.
As to claim 10, the modified system of Kim discloses the computer-readable medium of claim 8, wherein the data processing measurement is based on power up of an interface to the hardware resource in the reduced power state (Kim discloses PCIe communication between enhanced NIC 500 and processor 306, and Yao considers the time required to transfer workload data to a computing unit, Kim, Fig. 5A, paras. 0046–0047) and the hardware resource in the reduced power state (Kim accounts for wake-up latency when transitioning processor cores from reduced-power C states, paras. 0029–0031 and 0037–0039) to operate at a first level of processing (Kim’s Decision Engine 502 causes necessary processor cores to transition from a low-performance or sleep state to the P0 highest-performance state, Fig. 5A, paras. 0047–0048).
As to claim 11, the modified system of Kim discloses the computer-readable medium of claim 10, wherein the first level of processing comprises a data processing rate (Kim’s P0 state provides the processor’s highest operational voltage-and-frequency point, paras. 0025 and 0038) associated with a power consumption level (Kim’s processor-performance states are defined by operational voltage and frequency, with reduced voltage or frequency decreasing power consumption, para. 0025) that is higher than a power consumption level of the reduced power state (Kim’s idle, halt, sleep, and off C states consume reduced power, whereas NCAP transitions the processor to P0 and increases its operational frequency to the maximum, paras. 0029, 0047, and 0057).
As to claim 12, the modified system of Kim discloses the computer-readable medium of claim 8, wherein the available hardware resources comprise hardware resources (Yao’s available computing units include CPUs, GPUs, FPGAs, and accelerator processing units, Fig. 1, paras. 0015–0016 and 0023) enclosed in a casing that encompasses the network interface device (Yao discloses processors, DMA engine circuitry 352, queues, memory, and packet-allocation circuitry as components of NIC/IPU computing device 300, Fig. 3, paras. 0064–0067).
As to claim 13, the modified system of Kim discloses the computer-readable medium of claim 9, wherein the available hardware resources comprise hardware resources connected to the network interface device via an interface (Yao’s NIC/IPU communicates with host CPUs, accelerators, memory, and servers through a bus, PCIe, CXL, or other device interface, Figs. 1, 3, and 4, paras. 0032, 0064, 0075, and 0076) and hardware resources enclosed in a casing that encompasses the network interface device (Yao discloses local programmable processors, DMA engine circuitry 352, memory 310, and packet-allocation circuitry 324 as components of NIC/IPU computing device 300, Fig. 3, paras. 0064–0067).
As to claim 14, the modified system of Kim discloses the computer-readable medium of claim 8, wherein the select a hardware resource among the available hardware resources based on a data processing measurement for the particular operation (Yao selects a particular computing unit from multiple available computing units based on a comparison of their respective performance metrics and selects, based on those measurements, the unit capable of executing the particular workload most efficiently, Fig. 1, paras. 0015–0016 and 0041) is to prioritize use of a hardware resource in the network interface device (Yao’s performance-based resource-selection framework may be implemented in a NIC/IPU containing local programmable processors that perform CPU-offloaded operations and process received packets; selecting the NIC-local processor when its performance measurement identifies it as the most efficient available resource constitutes prioritizing use of a hardware resource in the network interface device, Figs. 1 and 3, paras. 0015–0016 and 0064–0067).
As to claim 15, the modified system of Kim discloses a computer-implemented method comprising: at a network interface device (Yao’s resource-selection processing circuitry may be implemented as a NIC, network interface card, IPU, or DPU, Fig. 3, paras. 0064–0067): based on a request to process data by a particular operation (Yao’s network packet 103 contains data associated with a workload such as encryption, decryption, compression, decompression, machine learning, or data I/O, and causes generation of an API call identifying the operation, Fig. 1, paras. 0012, 0014, and 0032–0033): determining available hardware resources (Yao’s framework identifies available CPUs and accelerator processing units and develops a mapping between workload parameters and computing units capable of executing the workload, Fig. 1, paras. 0015–0016, 0021, and 0033), wherein the available hardware resources include a hardware resource in a reduced power state (Kim’s available processor cores may occupy reduced-power C states including idle, halt, sleep, and off states, paras. 0029–0031) and selecting a hardware resource among the available hardware resources (Yao’s framework selects one computing unit from multiple available CPUs and accelerators to execute the requested workload, Fig. 1, paras. 0015–0016 and 0033) based on a data processing measurement for the particular operation (Yao selects the computing unit based on comparative performance metrics, including data-transfer time and workload-execution efficiency, and selects the unit determined based on those measurements to execute the particular workload most efficiently, Fig. 1, paras. 0015–0016 and 0041).
The rationale for combining Kim and Yao regarding claim 15 is substantially the same as set forth above for claim 1.
As to claim 16, the modified system of Kim discloses the method of claim 15, wherein the data processing measurement for the particular operation comprise one or more of (Yao’s comparative performance metrics determine which available computing unit most efficiently executes the particular workload, Fig. 1, paras. 0015–0016 and 0041): time (Yao considers the time required to transfer workload data to a computing unit, Fig. 1, para. 0016) or number of clock cycles to process data or priority level of hardware resource to process the data.
As to claim 17, the modified system of Kim discloses the method of claim 15, wherein the data processing measurement is based on power up of an interface to the hardware resource in the reduced power state (Kim discloses PCIe communication between enhanced NIC 500 and processor 306Fig. 5A, paras. 0046–0047) and the hardware resource in the reduced power state (Kim accounts for wake-up latency when transitioning processor cores from reduced-power C states, paras. 0029–0031 and 0037–0039) to operate at a first level of processing (Kim’s Decision Engine 502 causes necessary processor cores to transition from a low-performance or sleep state to the P0 highest-performance state, Fig. 5A, paras. 0047–0048).
As to claim 18, the modified system of Kim discloses the method of claim 15, wherein the available hardware resources comprise hardware resources (Yao’s available computing units include CPUs, GPUs, FPGAs, and accelerator processing units, Fig. 1, paras. 0015–0016 and 0023) enclosed in a casing that encompasses the network interface device (Yao discloses processors 304, DMA engine circuitry 352, memory 310, queues, and packet-allocation circuitry 324 as components of NIC/IPU computing device 300, Fig. 3, paras. 0064–0067).
As to claim 19, the modified system of Kim discloses the method of claim 15, wherein the available hardware resources comprise hardware resources (Yao’s available computing units include CPUs and accelerator processing units capable of executing packet-associated workloads, Fig. 1, paras. 0015–0016 and 0033) connected to the network interface device via an interface (Yao’s NIC/IPU communicates with host processors, accelerators, memory, and servers through a bus, PCIe, CXL, or other device interface, Figs. 1, 3, and 4, paras. 0032, 0064, 0075, and 0076).
As to claim 20, the modified system of Kim discloses the method of claim 15, wherein the selecting the hardware resource among the available hardware resources (Yao selects one computing unit from multiple available CPUs and accelerator processing units to execute the requested workload, Fig. 1, paras. 0015–0016 and 0033) based on a time to process the data by the particular operation (Yao selects the computing unit based on comparative performance metrics, including the time required to transfer workload data and the efficiency with which the unit executes the particular workload, Fig. 1, paras. 0015–0016 and 0041) is to prioritize use of a hardware resource in the network interface device (Yao’s performance-based resource-selection framework may be implemented in a NIC/IPU containing local programmable processors that perform CPU-offloaded operations and process received packets; selecting the NIC-local processor when its time-based performance measurement identifies it as the most efficient available resource constitutes prioritizing use of a hardware resource in the network interface device, Figs. 1 and 3, paras. 0015–0016 and 0064–0067).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Doshi et al. (US Pub. No. 20210117249) disclosed an Infrastructure Processing Unit (IPU) that comprises: interface circuitry to provide a communicative coupling with a platform; network interface circuitry to provide a communicative coupling with a network medium.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUANITO C BORROMEO whose telephone number is (571)270-1720. The examiner can normally be reached on Monday - Friday 9 - 5.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached on 5712724176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.C.B/ Assistant Examiner, Art Unit 2184
/HENRY TSAI/ Supervisory Patent Examiner, Art Unit 2184
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