DETAILED ACTION This Office Action is in response to the application filed on 01 August 2023. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election without traverse of claims 1-9 in the reply filed on 10 March 2026 is acknowledged. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-3, 5, and 6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (US 2023/0178552 A1; hereinafter Huang ). In regards to claim 1, Huang teaches a semiconductor device, comprising: a substrate (102) [0030] that includes an active pattern (108) [0033] ; a channel pattern (104) on the active pattern, the channel pattern including a plurality of semiconductor patterns (fig. 1A: e.g. the plurality of instances of (104)) that are spaced apart from and vertically stacked on each other (fig. 1A: instances of (104) are spaced apart from each other by (114) and (112) and form a vertical stack) ; a source/drain pattern connected to the plurality of semiconductor patterns each of which has a p-type conductivity [0031] ; a gate electrode on the plurality of semiconductor patterns, the gate electrode including inner electrodes (112) [0034] between neighboring ones of the plurality of semiconductor patterns and an outer electrode (116/117) on an uppermost semiconductor pattern of the plurality of semiconductor patterns (fig. 1A: (116/117) are on the side surfaces of the uppermost semiconductor pattern (106)) [0037] ; and a gate dielectric layer (114) [0035] between the gate electrode and the plurality of semiconductor patterns, the gate dielectric layer including an inner gate dielectric layer adjacent to the inner electrode and an outer gate dielectric layer (fig. 1A: (114) in contact with (116)) that extends from a bottom surface of the outer electrode to a lateral surface of the outer electrode (fig. 1A) , wherein the outer electrode and the outer gate dielectric layer have an inverted T shape [0016-0017] . In regards to claim 2, Huang teaches the limitations discussed above in addressing claim 1 . Huang further teaches the limitations wherein: the outer electrode includes a lower portion (116) and an upper portion (117) , the upper portion being on the lower portion (fig. 1A) , and the lower portion extends toward the source/drain pattern [0031] . In regards to claim 3, Huang teaches the limitations discussed above in addressing claim 1. Huang further teaches the limitations wherein: the outer electrode includes a lower portion (116) and an upper portion (117) on the lower portion, and a first width of the lower portion is greater than a second width of the upper portion (fig. 1A) . In regards to claim 5, Huang teaches the limitations discussed above in addressing claim 1. Huang further teaches the limitations wherein a portion of a lateral surface of the outer gate dielectric layer (114) is in direct contact with the source/drain pattern (fig. 1A: (114) in contact with (116)) . In regards to claim 6, Huang teaches the limitations discussed above in addressing claim 1. Huang further teaches the limitations further comprising a high-k dielectric layer between the gate electrode and the gate dielectric layer, wherein the high-k dielectric layer has a uniform thickness [0035] . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 4 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang as applied to claims 1 and 3 above. In regards to claim 4, Huang teaches the limitations discussed above in addressing claim 3 . Huang appears to be silent as to, but does not preclude, the limitations wherein the first width is greater than a width of each of the inner electrodes . Huang teaches the limitations of electrodes with respective widths that are optimized for contact resistances [0033] . Therefore, absent persuasive evidence, it would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to find that the configuration of an element is a matter of choice. In re Dailey , 357 F. 2d 669, 149 USPQ 47 (CCPA 1966). In regards to claim 9, Huang teaches the limitations discussed above in addressing claim 1 . Huang appears to be silent as to, but does not preclude, the limitations wherein a sidewall of the source/drain pattern has a wave-shape profile . Huang teaches the limitations of electrodes with respective widths that are optimized for contact resistances [0033] . Therefore, absent persuasive evidence, it would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to find that the configuration of an element is a matter of choice. In re Dailey , 357 F. 2d 669, 149 USPQ 47 (CCPA 1966). Claim(s) 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang as applied to claim 1 above, in view of Lilak et al. (US 2020/0006331 A1; hereinafter Lilak ). In regards to claim 7, Huang teaches the limitations discussed above in addressing claim 1 . Huang further teaches, e.g. in fig. 1A , the limitations further comprising: an active contact on the source/drain pattern [0031] ; and a gate contact (136) on the gate electrode [0043] , wherein: the gate contact is electrically connected to the gate electrode (fig. 1B: (136) is connected to (118)) , and a bottom surface of the gate contact is coupled to a top surface of the outer electrode of the gate electrode (fig. 1B) . Huang appears to be silent as to, but does not preclude, the limitations of a metal-semiconductor compound layer between the active contact and the source/drain pattern . Lilak teaches the limitations a metal-semiconductor compound layer between the active contact and the source/drain pattern [0033] . It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Huang with the aforementioned limitations taught by Lilak such that the source/drain active contacts are made of multiple materials to optimize the contact resistance to a source/drain ( Lilak [0033]) . In regards to claim 8, the combination of Huang and Lilak teaches the limitations discussed above in addressing claim 7 . Lilak teaches the limitations wherein the active contact includes: a conductive pattern [0033] ; a barrier pattern that surrounds the conductive pattern [0033] ; and an upper dielectric pattern on the conductive pattern and the barrier pattern [0033] . It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Huang with the aforementioned limitations taught by Lilak such that the source/drain active contacts are made of multiple materials to optimize the contact resistance to a source/drain ( Lilak [0033]) . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT CALVIN Y CHOI whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-7882 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F 8-4 (Pacific Time) . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice . 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. FILLIN "Examiner Stamp" \* MERGEFORMAT CALVIN CHOI Patent Examiner Art Unit 2812 /CALVIN Y CHOI/ Patent Examiner, Art Unit 2812