DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a response to the amendment filed 5/8/2026. Claims 1-20 are pending and are under examination.
The rejection of claim(s) 1, 5-8, 12-15 and 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Altaras et al. (US 2017/0126001) has been withdrawn in view of applicant’s remarks dated 5/8/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 8 and 15 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Fang et al. (USP 11,837,866).
Regarding claim 1, Fang et al.’s figure 4 shows A device comprising: an input-output stage (404) having first transistors (M2, M3) coupled between a voltage supply (ESD rail) and ground; and a power clamping stage (402) having resistor-capacitor circuitry (C0, R1) and second transistors (M1, M0), the resistor-capacitor circuitry coupled in parallel with the second transistors (M0, M1) between the voltage supply and ground, wherein during a power surging event, electro-static discharge is concurrently distributed across the first transistors (M2, M3) and the second transistors (M1, Mo) by way of passing from the voltage supply to ground (during power surging event, ESD being discharged to two discharging paths 404 and 402 at the same time; see column 6, lines 31-45, column 7, lines 60-65) as called for in claim 1.
Regarding claim 8, Fang et al.’s figure 4 shows A device comprising: an input-output stage having assist circuitry (C1, M3, R2) and driver circuitry (M2, R3) coupled between a voltage supply and ground; and a power clamping stage having triggering circuitry and a big field-effect transistor (M0) coupled between the voltage supply and ground, wherein during a power surging event, electro-static discharge is distributed across the driver circuitry when triggered by the assist circuitry, and wherein during the power surging event, the electro-static discharge is also concurrently distributed across the big field-effect transistor when triggered by the triggering circuitry (during power surging event, ESD being discharged to two discharging paths 404 and 402 at the same time; see column 6, lines 31-45) as called for in claim 8.
Regarding claim 15, Fang et al.’s figure 4 shows A method comprising: providing an input-output stage with assist circuitry (C1, M3, R2) and driver circuitry (M2, R3) coupled between a voltage supply and ground; and providing a power clamping stage with triggering circuitry and a big field-effect transistor (M0) coupled between the voltage supply and ground, during a power surging event, distributing electro-static discharge across the driver circuitry when triggered by the assist circuitry, and during the power surging event, distributing the electro-static discharge concurrently across the big field-effect transistor when triggered by the triggering circuitry (during power surging event, ESD being discharged to two discharging paths 404 and 402 at the same time; see column 6, line 31-45) as called for in claim 15.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-7, 12-14 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fang et al. (USP 11,837,866) in view of Baker (USP 6,483,347).
Regarding claims 5-6, 12-13 and 18-19 Fang et al.’s figure 4 shows a device comprising all the aspects of the present invention as noted in claim 1 or claim 8 or claim 15, except for the second transistors include a first triggering transistor and a second triggering transistor coupled in series between the voltage supply and ground; a first triggering node disposed between the resistor and the capacitor is coupled to gates of the first triggering transistor and the second triggering transistor as called for in claims 5-6, 12-13 and 18-19.
Fang et al.’s figure 4 shows an inverter composed of a transistor M1 and R0 instead of being first and second triggering transistors connected in series.
Baker’s figures 3A, 3D and 3E shows an inverter circuit can be formed either with a transistor and a resistor or a two transistors connected in series without altering the circuit operation. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to replace Fang et al.’s transistor M1 and resistor R0 with a two transistors inverter as taught by Baker’s figure 3A.
Regarding the recited functional limitation “wherein the electro-static discharge distributed across the first and second transistors corresponds to the same electro-static discharge event” (claim 5), it is seen that during a power surge event, both discharging paths are activated at the same time which enables ESD being discharged/distributed concurrently to the first and second transistors within the two discharging paths 404 and 402 (Column 6, lines 31-45; column 7, lines 60-67). Thus, the recited functional limitations “wherein the electro-static discharge distributed across the first and second transistors corresponds to the same electro-static discharge event” is also met.
Regarding claims 7, 14 and 20, the second transistors include a big field-effect transistor (M0) coupled in parallel with the first triggering transistor and the second triggering transistor between the voltage supply and ground, and a second triggering node disposed between the first triggering transistor and the second triggering transistor is coupled to a gate of the big field-effect transistor.
Response to Arguments
Applicant's arguments filed 5/8/2026 have been fully considered but they are not persuasive. Regarding the rejection of claims 1, 8 and 15 as being anticipated by Fang et al. (USP 11,837,866), applicant argues that Fang's disclosure is directed to providing multiple independent discharge paths within a power clamping stage. The cited paths (402 and 404) are parallel clamp branches that each independently conduct current from the supply to ground, thus, Fang does not disclose any structural or functional relationship in which electro-static discharge is distributed between two different sets of transistors belonging to different circuit stages. Claim 1 requires that electro-static discharge be concurrently distributed across the first transistors and the second transistors found not persuasive. Fang et al.’s Column 6, lines 31-45; column 7, lines 60-67 clearly suggests that during a power surging event, both discharging paths are activated at the same time which enables ESD being discharged/distributed concurrently to the first and second transistors within the two discharging paths 404 and 402. The rejection is deemed proper.
Dependent claims 5-7, 12-14 and 18-20 also remain rejected for the reasons noted above.
Allowable Subject Matter
Claims 2-4, 9-11 and 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TUAN T LAM/Primary Examiner, Art Unit 2836 7/11/2026
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