DETAILED ACTION
This action is responsive to: the amendment filed July 07, 2025. Claims 1-4, 7-11, and 14-18 are pending. Claims 5, 6, 12, 13, 19, and 20 are cancelled. Claims 1, 7, 8, and 14-17 have been amended. Claims 1, 8, and 15 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 07/07/2025 have been fully considered but they are not persuasive.
Applicant argues Chen does not disclose performing a hybrid erase operation that includes both an erase operation and a stripe erase operation subsequent to the erase operation.
Applicant’s arguments are not persuasive. Chen discloses in paragraph 139 that the memory cells are erased using the normal erase operation then followed by the stripe erase operation.
Applicant argues that the amendments to claim 1 overcome the Chen reference.
Applicant’s arguments are not persuasive. In paragraph 132 and 135-136, the Chen reference explains a hybrid process and the erase voltages sending two voltage pulses, one at 0 volts, the other at 0.5 volts and the voltage pulse being applied in figure 9: 902. Figure 13 shows a hybrid system as well as figure 12 shows a combination of a hybrid. The 102 rejection is maintained.
It is recommended that applicant point out a specific/distinct difference between the applicant’s hybrid process and Chen’s hybrid process.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by
Chen et al. (US 20220399066).
Regarding independent claim 1, Chen discloses a storage device (Fig. 1: 126a), comprising:
a non-volatile memory (Fig. 1:126) including control circuitry (Fig. 1: 110) and an array of memory cells (Fig. 1:126) formed using a set of word lines (Fig. 5A: WLL0-WLL9) and a set of bit lines (Fig. 1:132); and
a controller (Fig. 1: 122), coupled to the non-volatile memory (Fig. 1:126), configured to perform a hybrid erase operation (Fig. 9: 900, 12, and see paragraph 132 and 135 - 136) including both an erase operation (Fig. 9: 900) and a stripe erase operation (Figs. 10A - 10C, see para. 47) by:
performing the erase operation (Fig. 9: 900) including simultaneously erasing memory cells (Fig. 9: 900) associated with a block (Fig. 4: BLK), wherein the erase operation (Fig. 9: 900) includes (i) a first erase pulse (first erase voltage) having a first erase voltage (Fig. 9: 900) and (ii) a second erase pulse (Fig. 9: 902, showing the increase erase voltage 910 and then the apply erase conditions again at 902), following the first erase pulse (Fig. 9: 902), having a second erase voltage (Fig. 9: 900, showing there is more than one erase voltage) greater than the first erase voltage (Fig. 9: 900); and
subsequent to the second erase pulse (Fig. 9: 902, showing the increase erase voltage 910 and then the apply erase conditions again at 902) of the erase operation (Fig. 9, show the erase operation), performing the stripe erase operation (Figs. 10A - 10C, see para. 47) including simultaneously erasing memory cells (Fig. 9: 900) associated with every other wordline (Fig. 5A: WLL0-WLL9) of the block (Fig. 4: BLK) and then simultaneously erasing memory cells (Fig. 9: 900) associated with remaining wordlines (Fig. 5A: WLL0-WLL9) of the block (Fig. 4: BLK), wherein the stripe erase operation (Figs. 10A - 10C, see para. 47) includes (i) a third erase pulse (Fig. 9: 902), following the second erase pulse (Fig. 9: 902, showing the increase erase voltage 910 and then the apply erase conditions again at 902), having the second erase voltage (Fig. 9: 900, showing there is more than one erase voltage), and (ii) a fourth erase pulse (Fig. 9: 902, showing the increase erase voltage 910 and then the apply erase conditions again at 902), following the third erase pulse (Fig. 9: 902), having the second erase voltage (Fig. 9: 900, showing there is more than one erase voltage).
Regarding claim 2, Chen discloses wherein the controller (Fig. 1: 122) is further configured to:
perform a verify operation (Fig. 9:908) on the memory cells (Fig. 1:126) associated with the block (Fig. 4: BLK) after applying the first erase pulse (Fig. 9: 902) of the erase operation (Fig. 9: 900); and
in response to determining that the memory cells (Fig. 1:126) have completed erase (Fig. 9: 908, Yes, Done), perform the stripe erase operation (Figs. 10A - 10C, see para. 47).
Regarding claim 3, Chen discloses wherein the controller (Fig. 1: 122) is further configured to:
in response to determining that the memory cells (Fig. 1:126) have not completed erase (Fig. 9: 908, No, 910), apply the second erase pulse (Fig. 9: 902, showing the increase erase voltage 910 and then the apply erase conditions again at 902) of the erase operation (Fig. 9: 900).
Regarding claim 4, Chen discloses wherein the controller (Fig. 1: 122) is further configured to:
perform a verify operation (Fig. 9:908) on the memory cells (Fig. 1:126) associated with the block (Fig. 4: BLK) after the stripe erase operation (Figs. 10A - 10C, see para. 47); and
in response to determining that the memory cells (Fig. 1:126) have not completed erase (Fig. 9: 908, No, 910), perform another stripe erase operation (Figs. 10A - 10C, see para. 47).
Regarding claim 7, Chen discloses wherein the stripe erase operation (Figs. 10A - 10C, see para. 47) includes:
during the third erase pulse (Fig. 9: 902), biasing the every other wordline (Fig. 5A: WLL0-WLL9) of the block (Fig. 4: BLK) with a first bias (See para. 135, stating word line inhibit voltage) and biasing the remaining wordlines (Fig. 5A: WLL0-WLL9) of the block (Fig. 4: BLK) with a second bias (See para. 135, word lines erase voltage), wherein the first bias (See para. 135, stating word line inhibit voltage) is higher than the second bias (See para. 135, word lines erase voltage); and
during the fourth erase pulse (Fig. 9: 902, showing the increase erase voltage 910 and then the apply erase conditions again at 902), biasing the every other wordline (Fig. 5A: WLL0-WLL9) of the block (Fig. 4: BLK) with the second bias (See para. 135, word lines erase voltage) and biasing the remaining wordlines (Fig. 5A: WLL0-WLL9) of the block (Fig. 4: BLK) with the first bias (See para. 135, stating word line inhibit voltage).
Regarding independent claim 8, Chen discloses a method of operating a memory apparatus (Fig. 1: 100) including a plurality of memory cells (Fig. 1:126), the method comprising performing a hybrid erase operation (Fig. 9: 900, 12, and see paragraph 132 and 135 - 136) including both an erase operation (Fig. 9, showing an erase operation) and a stripe erase operation (Figs. 10A - 10C, see para. 47) by:
performing the erase operation (Fig. 9, showing an erase operation) including simultaneously erasing memory cells (Fig. 1:126) associated with a block (Fig. 4: BLK), wherein the erase operation (Fig. 9: 900) includes (i) a first erase pulse (Fig. 9: 902) having a first erase voltage (Fig. 9: 900) and (ii) a second erase pulse (Fig. 9: 902, showing the increase erase voltage 910 and then the apply erase conditions again at 902), following the first erase pulse (Fig. 9: 902), having a second erase voltage (Fig. 9: 900, showing there is more than one erase voltage) greater than the first erase voltage (Fig. 9: 900); and
subsequent to the second erase pulse (Fig. 9: 902, showing the increase erase voltage 910 and then the apply erase conditions again at 902) of the erase operation (Fig. 9: 900), performing the stripe erase operation (Figs. 10A - 10C, see para. 47) including simultaneously erasing memory cells (Fig. 1:126) associated with every other wordline of the block (Fig. 4: BLK) and then simultaneously erasing memory cells (Fig. 1:126) associated with remaining wordlines of the block (Fig. 4: BLK), wherein the stripe erase operation includes (i) a third erase pulse (Fig. 9: 902), following the second erase pulse (Fig. 9: 902, showing the increase erase voltage 910 and then the apply erase conditions again at 902), having the second erase voltage (Fig. 9: 900, showing there is more than one erase voltage), and (ii) a fourth erase pulse (Fig. 9: 902, showing the increase erase voltage 910 and then the apply erase conditions again at 902), following the third erase pulse (Fig. 9: 902), having the second erase voltage (Fig. 9: 900, showing there is more than one erase voltage).
Regarding claim 9, Chen discloses the method further including:
performing a verify operation (Fig. 9: 908) on the memory cells (Fig. 1:126) associated with the block (Fig. 4: BLK) after applying the first erase pulse (Fig. 9: 902) of the erase operation (Fig. 9: 900); and
in response to determining that the memory cells (Fig. 1:126) have completed erase (Fig. 9: 908, Yes, Done), performing the stripe erase operation (Figs. 10A - 10C, see para. 47).
Regarding claim 10, Chen discloses the method further including:
in response to determining that the memory cells (Fig. 1:126) have not completed erase (Fig. 9: 908, No, 910), applying the second erase pulse (Fig. 9: 902, showing the increase erase voltage 910 and then the apply erase conditions again at 902) of the erase operation (Fig. 9: 900).
Regarding claim 11, Chen discloses the method further including:
performing a verify operation (Fig. 9: 908) on the memory cells (Fig. 1:126) associated with the block (Fig. 4: BLK) after the stripe erase operation (Figs. 10A - 10C, see para. 47); and
in response to determining that the memory cells (Fig. 1:126) have not completed erase (Fig. 9: 908, No, 910), performing another stripe erase operation (Figs. 10A - 10C, see para. 47).
Regarding claim 14, Chen discloses wherein performing the stripe erase operation (Figs. 10A - 10C, see para. 47) includes:
during the third erase pulse (Fig. 9: 902), biasing the every other wordline of the block (Fig. 4: BLK) with a first bias (See para. 135, stating word line inhibit voltage) and biasing the remaining wordlines of the block (Fig. 4: BLK) with a second bias (See para. 135, word lines erase voltage), wherein the first bias (See para. 135, stating word line inhibit voltage) is higher than the second bias (See para. 135, word lines erase voltage); and
during the fourth erase pulse (Fig. 9: 902, showing the increase erase voltage 910 and then the apply erase conditions again at 902), biasing the every other wordline of the block (Fig. 4: BLK) with the second bias (See para. 135, word lines erase voltage) and biasing the remaining wordlines of the block (Fig. 4: BLK) with the first bias (See para. 135, stating word line inhibit voltage).
Regarding claim 15, Chen discloses an apparatus for performing a hybrid erase operation (Fig. 9: 900, 12, and see paragraph 132 and 135 - 136) including both an erase operation (Fig. 9: 900) and a stripe erase operation (Figs. 10A - 10C, see para. 47), the apparatus (Fig. 1:100) comprising:
a means for performing, as part of the hybrid erase operation (Fig. 9: 900, 12, and see paragraph 132 and 135 - 136), the erase operation (Fig. 9: 900), the erase operation (Fig. 9: 900) including simultaneously erasing memory cells (Fig. 1:126) associated with a block (Fig. 4: BLK), wherein the erase operation (Fig. 9: 900) includes (i) a first erase pulse (Fig. 9: 902) having a first erase voltage and (ii) a second erase pulse (Fig. 9: 902, showing the increase erase voltage 910 and then the apply erase conditions again at 902), following the first erase pulse (Fig. 9: 902), having a second erase voltage (Fig. 9: 900, showing there is more than one erase voltage) greater than the first erase voltage (Fig. 9: 900); and
a means for, subsequent to the second erase pulse (Fig. 9: 902, showing the increase erase voltage 910 and then the apply erase conditions again at 902) of the erase operation (Fig. 9: 900), performing the stripe erase operation (Figs. 10A - 10C, see para. 47), the stripe erase operation (Figs. 10A - 10C, see para. 47) including simultaneously erasing memory cells (Fig. 1:126) associated with every other wordline of the block (Fig. 4: BLK) and then simultaneously erasing memory cells (Fig. 1:126) associated with remaining wordlines of the block (Fig. 4: BLK), wherein the stripe erase operation (Figs. 10A - 10C, see para. 47) includes (i) a third erase pulse, following the second erase pulse, having the second erase voltage, and (ii) a fourth erase pulse (Fig. 9: 902, showing the increase erase voltage 910 and then the apply erase conditions again at 902), following the third erase pulse, having the second erase voltage.
Regarding claim 16, Chen discloses the apparatus (Fig. 1: 100) further comprising:
a means for performing a verify operation (Fig. 9: 908) on the memory cells (Fig. 1:126) associated with the block (Fig. 4: BLK) after applying the first erase pulse (Fig. 9: 902) of the erase operation (Fig. 9: 900); and
a means for performing the stripe erase operation (Figs. 10A - 10C, see para. 47) in response to determining that the memory cells (Fig. 1:126) have completed erase (Fig. 9: 908, Yes, Done).
Regarding claim 17, Chen discloses the apparatus (Fig. 1: 100) further comprising:
a means for applying the second erase pulse (Fig. 9: 902, showing the increase erase voltage 910 and then the apply erase conditions again at 902) of the erase operation (Fig. 9: 900) in response to determining that the memory cells (Fig. 1:126) have not completed erase (Fig. 9: 908, No, 910).
Regarding claim 18, Chen discloses the apparatus (Fig. 1: 100) further including:
a means for performing a verify operation (Fig. 9: 908) on the memory cells (Fig. 1:126) associated with the block (Fig. 4: BLK) after the stripe erase operation (Figs. 10A - 10C, see para. 47); and
a means for performing another stripe erase operation (Figs. 10A - 10C, see para. 47) in response to determining that the memory cells (Fig. 1:126) have not completed erase (Fig. 9: 908, No, 910).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRACY HAMPTON whose telephone number is (703)756-1091. The examiner can normally be reached Monday - Friday 8:30am - 5:00pm.
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/TRACY HAMPTON/ Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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