DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Amendment dated 06/12/2026 is acknowledged. Claims 1, 3, 7-9, 11, 15, 18-20 are amended. New claim 21 is added. Claim 4 is cancelled. Claims 1-3,5-21 remain pending in application.
Response to Arguments
Arguments filed 06/12/2026 are acknowledged. Amendments overcame rejections under 35 USC 112., set forth in previous office action Accordingly, associated 112(b) rejections of claims 8-9 & 19 are hereby withdrawn. Amendments overcome drawing objection, set forth in previous office action. Accordingly, associated drawing objections are hereby withdrawn. However, a new ground of rejection is made in current office action due to discovery of several 112(b) issues in claims 1-2, 5, 12-13, 19-21. Accordingly, previously indicated allowability of original claim 4 (which were incorporated in amended claim 1 , 19 & 20 ) are hereby withdrawn.
Examiner made several rounds of interview with applicant with proposed examiner amendment, but applicant finally disagreed on the proposed amendments on amended limitation “wherein, in a width direction of the boundary gate electrode, a width of the boundary insulating pattern is greater than a width of the gate contact portion and is less than a width of the boundary gate electrode” in claims 1 , 19 & 20. Since this amended limitation was the allowable subject matter of original claim 4 as indicated in previous office action, hence allowability of original claim 4 are withdrawn. Accordingly, this action is therefore made non-final.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3, 5-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites, “……., is electrically connected to a connection gate electrode among the plurality of gate electrodes, and is insulated from a remaining gate electrode by an insulating pattern between the remaining gate electrode and the gate contact portion”. It is not clear if it was intended to recite “……,is electrically connected to a connection gate electrode among the plurality of gate electrodes of the lower and upper structures, and is insulated from a remaining gate electrode among the plurality of gate electrodes of the lower and upper structures by an insulating pattern between the remaining gate electrode among the plurality of gate electrodes of the lower and upper structures and the gate contact portion” or not. Examiner is interpreting as such.
Claim 1 further recites, “…… to maintain an electrical connection path of the boundary gate electrode and has a different structure from that of the insulating pattern”. It is not clear if it was intended to recite “…….to maintain an electrical connection path of the boundary gate electrode among the plurality of gate electrodes of the lower structure and has a different structure from that of the insulating pattern” or not. Examiner is interpreting as such.
Claim 1 further recites, “wherein, in a width direction of the boundary gate electrode, a width of the boundary insulating pattern is greater than a width of the gate contact portion and is less than a width of the boundary gate electrode”. It is not clear if it was intended to recite “wherein, in a width direction of the boundary gate electrode among the plurality of gate electrodes of the lower structure, a [[width]] diameter of the boundary insulating pattern is greater than a [[width]] diameter of the gate contact portion and is less than a width of the boundary gate electrode among the plurality of gate electrodes of the lower structure” or not. Examiner is interpreting as such.
Claims 2-3, 5-18 & 21 are rejected being dependent on claim 1.
Claim 2 further recites, “wherein as viewed in a plan view, the boundary insulating pattern has a closed shape that does not cut the boundary gate electrode” . It is not clear if it was intended to recite “wherein as viewed in a plan view, the boundary insulating pattern has a closed shape that does not cut the boundary gate electrode among the plurality of gate electrodes of the lower structure” or not. Examiner is interpreting as such.
Claim 5 further recites, “wherein the boundary gate electrode at which the boundary insulating pattern is formed includes one or more boundary gate electrodes”. It is not clear if it was intended to recite “wherein the boundary gate electrode among the plurality of gate electrodes of the lower structure at which the boundary insulating pattern is formed includes one or more boundary gate electrodes among the plurality of gate electrodes of the lower structure”. Examiner is interpreting as such.
Claim 12 further recites, “…… and the boundary insulating pattern extends from an upper surface of the upper insulating layer to pass through the boundary gate electrode”. It is not clear if it was intended to recite “……. and the boundary insulating pattern extends from an upper surface of the upper insulating layer to pass through the boundary gate electrode among the plurality of gate electrodes of the lower structure”. Examiner is interpreting as such.
Claim 13 further recites, “wherein: an entire width of the boundary insulating pattern is 100 nm to 1,000 nm; or a peripheral width the boundary insulating pattern from an outer edge of the gate contact portion is 1 nm to 300 nm; or an entire depth of the boundary insulating pattern is 1 nm to 1,000 nm”. It is not clear if it was intended to recite “wherein: [[an entire width]] the diameter of the boundary insulating pattern is 100 nm to 1,000 nm; or a peripheral width from an outer edge of the boundary insulating pattern [[from]] to an outer edge of the gate contact portion is 1 nm to 300 nm; or an entire depth of the boundary insulating pattern is 1 nm to 1,000 nm” or not. Examiner is interpreting as such
Claim 19 recites, “…. to maintain an electrical connection path of the boundary gate electrode…... wherein, in a width direction of the boundary gate electrode, a width of the boundary insulating pattern is greater than a width of the gate contact portion and is less than a width of the boundary gate electrode”. It is not clear if it was intended to recite “…….to maintain an electrical connection path of the boundary gate electrode among the plurality of gate electrodes of the lower structure; ……… wherein, in a width direction of the boundary gate electrode among the plurality of gate electrodes of the lower structure, a [[width]] diameter of the boundary insulating pattern is greater than a [[width]] diameter of the gate contact portion and is less than a width of the boundary gate electrode among the plurality of gate electrodes of the lower structure” or not. Examiner is interpreting as such.
Claim 20 recites, “a gate contact portion that penetrates the plurality of gate electrodes to be electrically connected to the circuit region, is electrically connected to a connection gate electrode among the plurality of gate electrodes, and is insulated from a remaining gate electrode by an insulating pattern that is disposed between the remaining gate electrode and the gate contact portion; and a boundary insulating pattern that is partially formed in a boundary gate electrode among the plurality of gate electrodes of the lower structure adjacent to a boundary portion between the upper structure and the lower structure to surround the gate contact portion to maintain an electrical connection path of the boundary gate electrode and has a different structure from that of the insulating pattern, wherein, in a width direction of the boundary gate electrode, a width of the boundary insulating pattern is greater than a width of the gate contact portion and is less than a width of the boundary gate electrode, wherein, in a width direction of the boundary gate electrode, a width of the boundary insulating pattern is greater than a width of the gate contact portion and is less than a width of the boundary gate electrode” .
It is not clear if it was intended to recite “a gate contact portion that penetrates the plurality of gate electrodes of the lower and upper structures to be electrically connected to the circuit region, is electrically connected to a connection gate electrode among the plurality of gate electrodes of the lower and upper structures, and is insulated from a remaining gate electrode among the plurality of gate electrodes of the lower and upper structures by an insulating pattern that is disposed between the remaining gate electrode among the plurality of gate electrodes of the lower and upper structures and the gate contact portion; and a boundary insulating pattern that is partially formed in a boundary gate electrode among the plurality of gate electrodes of the lower structure adjacent to a boundary portion between the upper structure and the lower structure to surround the gate contact portion to maintain an electrical connection path of the boundary gate electrode among the plurality of gate electrodes of the lower structure and has a different structure from that of the insulating pattern, wherein, in a width direction of the boundary gate electrode among the plurality of gate electrodes of the lower structure, a width of the boundary insulating pattern is greater than a width of the gate contact portion and is less than a width of the boundary gate electrode among the plurality of gate electrodes of the lower structure, wherein, in a width direction of the boundary gate electrode among the plurality of gate electrodes of the lower structure, a [[width]] diameter of the boundary insulating pattern is greater than a [[width]] diameter of the gate contact portion and is less than a width of the boundary gate electrode among the plurality of gate electrodes of the lower structure” or not. Examiner is interpreting as such.
Claim 21 further recites, wherein a lower surface of the boundary insulating pattern is lower than a lower surface of the boundary gate electrode and higher than an upper surface of a gate electrode among the plurality of gate electrodes that is adjacent to the boundary gate electrode”. It is not clear if it was intended to recite “wherein a lower surface of the boundary insulating pattern is lower than a lower surface of the boundary gate electrode among the plurality of gate electrodes of the lower structure and higher than an upper surface of a gate electrode among the plurality of gate electrodes that is adjacent to the boundary gate electrode among the plurality of gate electrodes of the lower structure” or not. Examiner is interpreting as such.
Allowable Subject Matter
Claims 1-3, 5-21 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
With respect to claims 1, 19 & 20 the prior art of record does not appear to teach, suggest, or provide motivation for combination to following limitation:
“wherein, in a width direction of the boundary gate electrode among the plurality of gate electrodes of the lower structure, a [[width]] diameter of the boundary insulating pattern is greater than a [[width]] diameter of the gate contact portion and is less than a width of the boundary gate electrode among the plurality of gate electrodes of the lower structure” (see 112(b) interpretation above).
Regarding claim 1, Kim teaches,
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A semiconductor device (Fig. 3A as annotated above) comprising:
a first substrate (5, para [0038]);
a circuit region including a peripheral circuit structure (3,para [0037]) on the first substrate;
and a cell region (structure above 3) that is disposed on the circuit region and includes a cell array region (comprising memory vertical structure 81 , para [0034), see as marked above) and a connection region (as marked), wherein the cell region includes:
a second substrate (24, para [0034]);
a gate stacking structure (ST’, para [0035]) that is on the second substrate and includes a lower structure (LS’) and an upper structure (US’), the lower structure and the upper structure each including a plurality of gate electrodes (115 including 115L & 115U, para [0056]);
a channel structure (85, para [0092]) penetrating the gate stacking structure;
a gate contact portion (136_2 as marked) that penetrates the gate stacking structure and is electrically connected to the circuit region, is electrically connected (via 136_E) to a connection gate electrode (115L as marked, third 115L from top of stack LS’) among the plurality of gate electrodes,
and is insulated from a remaining gate electrode (other gate electrodes 115L below the connection gate electrode in the lower stack LS’ ) by an insulating pattern (40a, FIG. 3C) between the remaining gate electrode and the gate contact portion (as seen);
and a boundary insulating pattern (including portion 40a in topmost 115L, 38U & 47 as marked) that is partially in a boundary gate electrode (portion 40a in topmost 115L as the boundary gate electrode) among the plurality of gate electrodes of the lower structure adjacent to a boundary portion (including 62L) between the upper structure and the lower structure to surround the gate contact portion (portion 47 surrounds the gate contact portion)
to maintain an electrical connection path of the boundary gate electrode (even though Kim does not illustrate the gate electrodes in plan view, there must be a current path (i.e. electrical connection path) between the boundary gate contact portion 136_2, see as marked, and the boundary gate electrodes in the cell region to the left in Fig. 3A above).
and has a different structure from that of the insulating pattern (the boundary insulating pattern includes 38U & 47 in addition to 40a and hence is different structures from that of 40a).
But Kim fails to teach,
wherein, in a width direction of the boundary gate electrode among the plurality of gate electrodes of the lower structure, a [[width]] diameter of the boundary insulating pattern is greater than a [[width]] diameter of the gate contact portion and is less than a width of the boundary gate electrode among the plurality of gate electrodes of the lower structure.
Regarding claim 19, Kim teaches,
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A semiconductor device (Fig. 3A as annotated above) comprising:
a first substrate (5, para [0038]);
a circuit region (3,para [0037]) including a peripheral circuit structure on the first substrate;
and a cell region (structure above 3) that is on the circuit region and includes a cell array region (comprising memory vertical structure 81 , para [0034) as marked) and a connection region (as marked),
wherein the cell region includes:
a second substrate (24, para [0034]);
a gate stacking structure (ST’) that is on the second substrate and includes a lower structure (LS’) and an upper structure (US’),
wherein the lower structure and the upper structure each include a plurality of gate electrodes (115 including 115L & 115U, para [0056]);
a channel structure (85, para [0092]) penetrating the gate stacking structure;
a gate contact portion (136_2 as marked) that penetrates the gate stacking structure to be electrically connected to the circuit region;
and a boundary insulation pattern (including portion 40a (in topmost 115L) , 38U & 47 as marked) that is partially formed in a boundary gate electrode (portion 40a in topmost 115L) among the plurality of gate electrodes of the lower structure adjacent to a boundary portion (62L) between the upper structure and the lower structure to surround the gate contact portion (portion 47 surrounds the gate contact portion)
to maintain an electrical connection path of the boundary gate electrode(even though Kim does not illustrate the gate electrodes in plan view, there must be a current path (i.e. electrical connection path) between the boundary gate contact portion 136_2, see as marked, and the boundary gate electrodes in the cell region to the left in Fig. 3A above) ;
and wherein an entire side surface of the boundary insulating pattern includes an inclined surface that gradually decreases in width toward the second substrate or a vertical surface perpendicular to the second substrate when the boundary insulating pattern is viewed in a cross-section (as seen 40a, 38U & 47 is vertical to substrate 24).
But Kim fails to teach,
wherein, in a width direction of the boundary gate electrode among the plurality of gate electrodes of the lower structure, a [[width]] diameter of the boundary insulating pattern is greater than a [[width]] diameter of the gate contact portion and is less than a width of the boundary gate electrode among the plurality of gate electrodes of the lower structure.
Regarding claim 20, Kim teaches,
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…..a main substrate (5, FIG. 3A as annotated above, para [0038]);
a semiconductor device (memory device as shown in Fig. 3A) on the main substrate;
……..wherein the semiconductor device includes a circuit region (3,para [0037]) including a peripheral circuit structure (11 & 13 , para [0038]) on a first substrate and a cell region (structure above 3) that is disposed on the circuit region and includes a cell array region (comprising memory vertical structure 81 , para [0034] as marked) and a connection region (as marked),
and wherein the cell region includes:
a second substrate (24, para [0034);
a gate stacking structure (ST’) that is on the second substrate and includes a lower structure (LS’) and an upper structure (US’),
wherein the lower structure and the upper structure each include a plurality of gate electrodes (115 including 115L & 115U, para [0056]);
a channel structure (85, para [0092]) penetrating the gate stacking structure;
a gate contact portion (136_2 as marked) that penetrates the plurality of gate electrodes to be electrically connected to the circuit region, is electrically connected (via 136_E) to a connection gate electrode (115L as marked, third 115L from top of stack LS’) among the plurality of gate electrodes, and is insulated from a remaining gate electrode (other gate electrodes 115L below the connection gate electrode in the lower stack LS’ ) by an insulating pattern (40a, FIG. 3C, para [0229]) that is disposed between the remaining gate electrode and the gate contact portion (as seen);
and a boundary insulating pattern (including portion 40a (in topmost 115L), 38U & 47 as marked) that is partially formed in a boundary gate electrode (portion 40a in topmost 115L) among the plurality of gate electrodes of the lower structure adjacent to a boundary portion (62L) between the upper structure and the lower structure to surround the gate contact portion (portion 47 surrounds the gate contact portion)
to maintain an electrical connection path of the boundary gate electrode (even though Kim does not illustrate the gate electrodes in plan view, there must be a current path (i.e. electrical connection path) between the boundary gate contact portion 136_2 and the boundary gate electrodes in the cell region to the left in Fig. 3A above).
But Kim does not explicitly teach,
An electronic system comprising: the main substrate and a controller electrically connected to the semiconductor device on the main substrate.
But Kim additionally teaches,
An electronic system (data storage system 1000, Fig. 27, para [0242]) comprising: a main substrate (substrate of 1100); a semiconductor device (1100) on the main substrate and a controller (1200) electrically connected to the semiconductor device (1100) on the main substrate.
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to incorporate the teaching of Kim above into the semiconductor device , in order to (for the purpose of) form a data storage system (i.e. data storage system 1000 including the semiconductor device of FIG. 3A/1100 on main substrate 5), as taught by Kim.
Kim still fails to teach,
wherein, in a width direction of the boundary gate electrode among the plurality of gate electrodes of the lower structure, a [[width]] diameter of the boundary insulating pattern is greater than a [[width]] diameter of the gate contact portion and is less than a width of the boundary gate electrode among the plurality of gate electrodes of the lower structure.
Claims 2-3, 5-18 & 21 would be allowable being dependent on claim 1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHATIB A RAHMAN whose telephone number is (571)270-0494. The examiner can normally be reached on MON-FRI 8:00 am- 5:00 pm (Arizona).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor Steven Loke, can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.A.R/Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
