DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims.
Each of claims 8 (ll. 2-4) and claim 19 (ll. 19-21) recites “….an entire side surface of the boundary insulating pattern includes an inclined surface that gradually decreases in width toward the second substrate” which is not shown in drawing. Therefore, the limitation ”…includes an inclined surface that gradually decreases in width toward the second substrate” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Claim 9 recites “wherein a side surface of the insulating pattern has a slope that is smaller than a slope of the boundary insulating pattern” which is not shown in drawing. Therefore, the limitation ”a side surface of the insulating pattern has a slope that is smaller than a slope of the boundary insulating pattern” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-9 & 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites, “wherein when the boundary insulating pattern is viewed in a cross-section, an entire side surface of the boundary insulating pattern includes an inclined surface that gradually decreases in width toward the second substrate” which is not clearly understood from Fig. 7 of disclosure, which appears to show width of side surface of 132p is constant and not gradually decreasing towards the second substrate. For examination purpose, examiner is considering boundary insulating pattern includes a vertical surface instead and accordingly, interpreting the limitation as “wherein when the boundary insulating pattern is viewed in a cross-section, an entire side surface of the boundary insulating pattern [[includes an inclined surface that gradually decreases in width toward the second substrate or that ]] includes a vertical surface perpendicular to the second substrate”.
Claim 9 recites, “wherein a side surface of the insulating pattern has a slope that is smaller than a slope of the boundary insulating pattern” which is not clearly understood from Fig. 7 of drawing. For examination purpose, examiner is interpreting the limitation as “wherein a side surface of the insulating pattern [[has a slope that is smaller than a slope of the boundary insulating pattern, or ]] includes a convex shape or a rounded portion” as per fig. 7 of drawing.
Claim 19 recites, “wherein an entire side surface of the boundary insulating pattern includes an inclined surface that gradually decreases in width toward the second substrate…… when the boundary insulating pattern is viewed in a cross-section” which is not clearly understood from Fig. 7 of disclosure which appears to show width of side surface of 132p is constant and not gradually decreasing towards the second substrate. For examination purpose, examiner is considering boundary insulating pattern includes a vertical surface instead and interpreting the limitation as “wherein an entire side surface of the boundary insulating pattern includes [[an inclined surface that gradually decreases in width toward the second substrate or]] a vertical surface perpendicular to the second substrate when the boundary insulating pattern is viewed in a cross-section”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-8,11-12, 14-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2022/0139831 A1).
Regarding claim 1, Kim teaches,
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A semiconductor device (Fig. 3A as annotated above) comprising:
a first substrate (5, para [0038]);
a circuit region including a peripheral circuit structure (3,para [0037]) on the first substrate;
and a cell region (structure above 3) that is disposed on the circuit region and includes a cell array region (comprising memory vertical structure 81 , para [0034), see as marked above) and a connection region (as marked), wherein the cell region includes:
a second substrate (24, para [0034]);
a gate stacking structure (ST’, para [0035]) that is on the second substrate and includes a lower structure (LS’) and an upper structure (US’), the lower structure and the upper structure each including a plurality of gate electrodes (115 including 115L & 115U, para [0056]);
a channel structure (85, para [0092]) penetrating the gate stacking structure;
a gate contact portion (136_2 as marked) that penetrates the gate stacking structure and is electrically connected to the circuit region, is electrically connected (via 136_E) to a connection gate electrode (115L as marked, third 115L from top of stack LS’) among the plurality of gate electrodes,
and is insulated from a remaining gate electrode (other gate electrodes 115L below the connection gate electrode in the lower stack LS’ ) by an insulating pattern (40a, FIG. 3C) between the remaining gate electrode and the gate contact portion (as seen);
and a boundary insulating pattern (including portion 40a in topmost 115L, 38U & 47 as marked) that is partially in a boundary gate electrode (portion 40a in topmost 115L as the boundary gate electrode) among the plurality of gate electrodes of the lower structure adjacent to a boundary portion (including 62L) between the upper structure and the lower structure to surround the gate contact portion (portion 47 surrounds the gate contact portion)
to maintain an electrical connection path of the boundary gate electrode (even though Kim does not illustrate the gate electrodes in plan view, there must be a current path (i.e. electrical connection path) between the boundary gate contact portion 136_2, see as marked, and the boundary gate electrodes in the cell region to the left in Fig. 3A above).
and has a different structure from that of the insulating pattern (the boundary insulating pattern includes 38U & 47 in addition to 40a and hence is different structures from that of 40a).
Regarding claim 2, Kim teaches the semiconductor device of claim 1 and further teaches, wherein as viewed in a plan view, the boundary insulating pattern has a closed shape that does not cut the boundary gate electrode (portion 40a surrounds (hence closed shape) the boundary gate contact portion 136_2 as marked above and must not cut the boundary gate electrode to maintain current path from the boundary gate contact pattern 136_2 to the boundary gate electrodes in cell region in left of FIG. 3A).
Regarding claim 3, Kim teaches the semiconductor device of claim 2 and further teaches, wherein as viewed in a plan view, the boundary insulating pattern has a circular, polygonal, or line shape (in view of FIG. FIG. 2A , which shows 115i which includes 40a, para [0229], is linear shape).
Regarding claim 5, Kim teaches the semiconductor device of claim 1 and further teaches,wherein the boundary gate electrode at which the boundary insulating pattern is formed includes one or more boundary gate electrodes (boundary gate electrode 115U as marked above).
Regarding claim 6, Kim teaches the semiconductor device of claim 1 and further teaches,wherein the boundary insulating pattern and the insulating pattern are made of different materials (40/40a made of silicon nitride , para [0205]) and 47 made of silicon oxide, para [0198]).
Regarding claim 7, Kim teaches the semiconductor device of claim 6 and further teaches, wherein: the boundary insulating pattern includes an insulating material of a single composition, and the insulating pattern is formed of a plurality of insulating layers, or includes a step (40a and 38U forms a step) or a portion of a blocking layer or a portion of the gate electrode at an upper or lower surface of the insulating pattern.
Regarding claim 8, Kim teaches the semiconductor device of claim 1 and further teaches, wherein when the boundary insulating pattern is viewed in a cross-section, an entire side surface of the boundary insulating pattern includes an inclined surface that gradually decreases in width toward the second substrate or that includes a vertical surface perpendicular to the second substrate (as seen 40a, 38U and 47 are vertical to substrate 24).
Regarding claim 11, Kim teaches the semiconductor device of claim 1 but does not explicitly teach, wherein: the boundary insulating pattern has a vertical etching and filling structure extending from an upper portion of the lower structure toward the second substrate, and the insulating pattern has a horizontal etching structure etched in a horizontal direction and a horizontal filling structure filled in a horizontal direction.
However, the limitation "a vertical etching and filling structure" and ‘a horizontal etching and filling structure...” is merely a product-by-process limitation that does not structurally distinguish the claimed invention over the prior art. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 227 USPQ 964, 966.
Regarding claim 12, Kim teaches the semiconductor device of claim 1 and further teaches, wherein: the lower structure includes an upper insulating layer (38U) at the boundary portion bonded to the upper structure, and the boundary insulating pattern extends from an upper surface of the upper insulating layer to pass through the boundary gate electrode (portion 40a of the boundary insulating pattern pass through the boundary gate electrode i.e. topmost 115L).
Regarding claim 14, Kim teaches the semiconductor device of claim 1 and further teaches,wherein an entire depth of the boundary insulating pattern (depth of 38U & 40a from top surface of 38U/47) is greater than a peripheral width of the boundary insulating pattern from an outer edge of the gate contact portion (width of 47 on 136E).
Regarding claim 15, Kim teaches the semiconductor device of claim 1 and further teaches, wherein: the boundary insulating pattern is at a portion (portion 40a of the boundary gate insulating pattern is at the boundary gate electrode 115L as marked) where an electrical connection path must be maintained and the boundary insulating pattern is between the cell array region and a pad area to which another gate contact portion is connected (as seen).
Regarding claim 16, Kim teaches the semiconductor device of claim 1 and further teaches,wherein: the semiconductor device includes a dummy structure penetrating the gate stacking structure in the connection region and the boundary insulating pattern is formed to surround the dummy structure along with the gate contact portion; or the gate contact portion includes a plurality of gate contact portions (plurality of 136_2) , and the boundary insulating pattern is formed to surround the plurality of gate contact portions (portion 47 of the boundary insulting pattern surrounds plurality of 136_2)
Regarding claim 17, Kim teaches the semiconductor device of claim 1 and further teaches, further comprising a cutting insulating pattern (47) that is formed to cut at least one gate electrode among a plurality of gate electrodes corresponding to a pad area to which another gate contact portion different from the gate contact portion is connected.
Regarding claim 18, Kim teaches the semiconductor device of claim 1 and further teaches, wherein: the gate stacking structure includes a first gate stacking structure (lower half of gate layers 115L in LS’) disposed on the second substrate (24), a second gate stacking structure (upper half of gate layers 115L in LS’) disposed on the first gate stacking structure to from the lower structure (LS’), and a third gate stacking structure (gate stack 115U in US’) disposed on the second gate stacking structure to form the upper structure (US’), the connection region includes first, second, and third pad areas (136E) to which the first, second, and third gate stacking structures and the gate contact portion are connected, respectively, the first, second, and third pad areas are sequentially disposed in a direction away from the cell array region (as seen), and the boundary insulating pattern is formed at the boundary gate electrode of the second gate stacking structure (upper half of 115L in LS’ as defined) adjacent to a boundary portion (62L) between the third gate stack structure and the second gate stacking structure in the first pad area (as seen)
Regarding claim 19, Kim teaches,
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A semiconductor device (Fig. 3A as annotated above) comprising:
a first substrate (5, para [0038]);
a circuit region (3,para [0037]) including a peripheral circuit structure on the first substrate;
and a cell region (structure above 3) that is on the circuit region and includes a cell array region (comprising memory vertical structure 81 , para [0034) as marked) and a connection region (as marked),
wherein the cell region includes:
a second substrate (24, para [0034]);
a gate stacking structure (ST’) that is on the second substrate and includes a lower structure (LS’) and an upper structure (US’),
wherein the lower structure and the upper structure each include a plurality of gate electrodes (115 including 115L & 115U, para [0056]);
a channel structure (85, para [0092]) penetrating the gate stacking structure;
a gate contact portion (136_2 as marked) that penetrates the gate stacking structure to be electrically connected to the circuit region;
and a boundary insulating pattern (including portion 40a (in topmost 115L) , 38U & 47 as marked) that is partially formed in a boundary gate electrode (portion 40a in topmost 115L) among the plurality of gate electrodes of the lower structure adjacent to a boundary portion (62L) between the upper structure and the lower structure to surround the gate contact portion (portion 47 surrounds the gate contact portion)
to maintain an electrical connection path of the boundary gate electrode(even though Kim does not illustrate the gate electrodes in plan view, there must be a current path (i.e. electrical connection path) between the boundary gate contact portion 136_2, see as marked, and the boundary gate electrodes in the cell region to the left in Fig. 3A above) ;
and wherein an entire side surface of the boundary insulating pattern includes an inclined surface that gradually decreases in width toward the second substrate or a vertical surface perpendicular to the second substrate when the boundary insulating pattern is viewed in a cross-section (as seen 40a, 38U & 47 is vertical to substrate 24).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically teaches d as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al US 20220139831 A1
Regarding claim 20, Kim teaches,
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…..a main substrate (5, FIG. 3A as annotated above, para [0038]);
a semiconductor device (memory device as shown in Fig. 3A) on the main substrate;
……..wherein the semiconductor device includes a circuit region (3,para [0037]) including a peripheral circuit structure (11 & 13 , para [0038]) on a first substrate and a cell region (structure above 3) that is disposed on the circuit region and includes a cell array region (comprising memory vertical structure 81 , para [0034] as marked) and a connection region (as marked),
and wherein the cell region includes:
a second substrate (24, para [0034);
a gate stacking structure (ST’) that is on the second substrate and includes a lower structure (LS’) and an upper structure (US’),
wherein the lower structure and the upper structure each include a plurality of gate electrodes (115 including 115L & 115U, para [0056]);
a channel structure (85, para [0092]) penetrating the gate stacking structure;
a gate contact portion (136_2 as marked) that penetrates the plurality of gate electrodes to be electrically connected to the circuit region, is electrically connected (via 136_E) to a connection gate electrode (115L as marked, third 115L from top of stack LS’) among the plurality of gate electrodes, and is insulated from a remaining gate electrode (other gate electrodes 115L below the connection gate electrode in the lower stack LS’ ) by an insulating pattern (40a, FIG. 3C, para [0229]) that is disposed between the remaining gate electrode and the gate contact portion (as seen);
and a boundary insulating pattern (including portion 40a (in topmost 115L), 38U & 47 as marked) that is partially formed in a boundary gate electrode (portion 40a in topmost 115L) among the plurality of gate electrodes of the lower structure adjacent to a boundary portion (62L) between the upper structure and the lower structure to surround the gate contact portion (portion 47 surrounds the gate contact portion)
to maintain an electrical connection path of the boundary gate electrode (even though Kim does not illustrate the gate electrodes in plan view, there must be a current path (i.e. electrical connection path) between the boundary gate contact portion 136_2 and the boundary gate electrodes in the cell region to the left in Fig. 3A above).
But Kim does not explicitly teach,
An electronic system comprising: the main substrate and a controller electrically connected to the semiconductor device on the main substrate.
But Kim additionally teaches,
An electronic system (data storage system 1000, Fig. 27, para [0242]) comprising: a main substrate (substrate of 1100); a semiconductor device (1100) on the main substrate and a controller (1200) electrically connected to the semiconductor device (1100) on the main substrate.
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to incorporate the teaching of Kim above into the semiconductor device , in order to (for the purpose of) form a data storage system (i.e. data storage system 1000 including the semiconductor device of FIG. 3A/1100 on main substrate 5), as taught by Kim.
Allowable Subject Matter
Claims 4, 10 & 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
With respect to claims 4, 10 & 13, the prior art of record does not appear to teach, suggest, or provide motivation for combination to following limitation:
wherein, in a width direction of the boundary gate electrode, a width of the boundary insulating pattern is greater than a width of the gate contact portion and is less than a width of the boundary gate electrode (claim 4).
wherein: the insulating pattern includes a void extending in a horizontal direction, and the boundary insulating pattern does not include a void or includes a void extending in a vertical direction (claim 10).
wherein: an entire width of the boundary insulating pattern is 100 nm to 1,000 nm; or a peripheral width of the boundary insulating pattern from an outer edge of the gate contact portion is 1 nm to 300 nm; or an entire depth of the boundary insulating pattern is 1 nm to 1,000 nm (claim 13).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHATIB A RAHMAN whose telephone number is (571)270-0494. The examiner can normally be reached on MON-FRI 8:00 am- 5:00 pm (Arizona).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor Steven Gauthier, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.A.R/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813