Prosecution Insights
Last updated: April 19, 2026
Application No. 18/229,652

BUFFER CIRCUIT

Non-Final OA §102§112
Filed
Aug 02, 2023
Examiner
SHAMIRYAN, NAREH
Art Unit
2843
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Analog Devices International Unlimited Company
OA Round
1 (Non-Final)
95%
Grant Probability
Favorable
1-2
OA Rounds
3y 2m
To Grant
99%
With Interview

Examiner Intelligence

Grants 95% — above average
95%
Career Allow Rate
41 granted / 43 resolved
+27.3% vs TC avg
Moderate +6% lift
Without
With
+6.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
22 currently pending
Career history
65
Total Applications
across all art units

Statute-Specific Performance

§103
41.4%
+1.4% vs TC avg
§102
26.8%
-13.2% vs TC avg
§112
28.2%
-11.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 43 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claim 12 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in a phone call with the attorney of record Robert Esposito Reg. No. 65071 on 12/09/2025. Priority Foreign priority is not claimed for this application. Information Disclosure Statement The information disclosure statements (IDS) submitted on 08/16/2023 and 12/24/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner. Drawings The drawings (specifically figures 4a, 4c, and 7) are not of sufficient quality to permit examination. Accordingly, replacement drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to this Office action. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. Applicant is given a shortened statutory period of TWO (2) MONTHS to submit new drawings in compliance with 37 CFR 1.81. Extensions of time may be obtained under the provisions of 37 CFR 1.136(a) but in no case can any extension carry the date for reply to this letter beyond the maximum period of SIX MONTHS set by statute (35 U.S.C. 133). Failure to timely submit replacement drawing sheets will result in ABANDONMENT of the application. Figures 1 and 2 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters “MP1-MP4” and “MN1-MN6” has been used to designate different transistors in Fig. 2-3 and Fig. 4a, 4c, 4d, and 7. The transistors labelled in this way in fig. 4a, 4c, 4d, and 7 represent transistors in the programmable/variable current source, however the transistors labelled in this way in fig. 2 and 3 represent transistors in different parts of the circuit, separate from the programmable/variable current source. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Objections Claims 2-11 and 14-20 are objected to because of the following informalities: Claims 2-11: the preambles of these claims should read “the buffer amplifier circuit of” instead of “the circuit of.” Claims 14-20: the preambles of these claims should read “the current source circuit of” instead of “the circuit of.” Claim 9, line 9: “replica bias circuit” should read “replica bias circuit subsystem” Claim 18: the preamble should read “the current source circuit of claim 13” instead of “the circuit of clause 13” Claim 20, line 3: “such as operational amplifier” should read “such as an operational amplifier” Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-11 and 13-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitation "the variable load" in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. Throughout the rest of this claim, the limitations simply refer to “the load.” This makes the claim clear unclear and indefinite, as examiner is unsure if “load” and “variable load” are different things. Appropriate correction is required. Claims 2-11, which are dependent on 1, inherit this rejection. Claim 1 also recites the limitation “…address the current requirements of…” This should be “…address current requirements of…” as this is the first mention of current requirements and is an antecedent basis issue. Appropriate correction is required. Claim 1 also states “a driver that supplies current” however, it’s not clear from the drawings or the specification which components make up the driver, and because of this, it makes claim 1 unclear and indefinite. Appropriate correction is required. Claim 2 recites the limitation "the output stage" in line 1. There is insufficient antecedent basis for this limitation in the claim. Appropriate correction is required. Claim 9 recites the limitation “the components within the replica components subsystem…. the components withing the first components subsystem” in lines 10-11. There is insufficient antecedent basis for this limitation in the claim. Examiner proposes changing “the components” to just “components.” Claims 10-11, which depend on claim 9, inherit this rejection. Claim 13 lines 6-7 have the same issue as claim 9. Claims 14-20, which depend on claim 13, inherit this rejection. Appropriate correction is required. Claim 14 recites the limitations "the control terminal voltage" and “the control terminal voltage” in lines 1-2. There is insufficient antecedent basis for these limitations in the claim. Appropriate correction is required. Claim 19 recites the limitations “the source of a transistor device” in line 1, “the drain” in line two and “the gate of the source follower” in lines 3-4. There is insufficient antecedent basis for these limitations in the claim. Appropriate correction is required. Claim 20 recites the limitations “the source of one or more transistor devices” in lines 1-2 and “the drains of the cascodes” in line 2. There is insufficient antecedent basis for these limitations in the claim. Appropriate correction is required. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-3 and 5-8 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by “Replica-Based Low Drop-Out Voltage Regulator with Assistant Power Transistors for Digital VLSI Systems” by Nan et al. Regarding claim 1, Nan teaches a buffer amplifier circuit (Fig. 2), comprising: a driver (Fig. 2 MP) that supplies current to a load in dependence on a voltage on the variable load (Fig. 2 Cout and R3); at least one variable current source, the variable current source being arranged in use to supply current to the variable load (Fig. 2 the array structure consisting of B1, SW1, SW2, and AP1); and a control input receiving control information pertaining to a current demand of the load (Fig. 2 the current sensor outputs Isense to a current comparator which outputs control information to the array of variable current sources); and wherein the at least one variable current source is controlled in dependence on the received control information to vary its output current such that current from the driver and the variable current source address the current requirements of the load, with at least a majority of the current requirements of the load being supplied by the variable current source (Page 7 Col. 1). Regarding claim 2, Nan teaches the circuit of claim 1, wherein the driver (Fig. 2 MP) is the output stage of an operational amplifier (Fig. 2 EA). Regarding claim 3, Nan teaches the circuit of claim 1, wherein the driver (Fig. 2 MP) is separate from the at least one variable current source(Fig. 2 the array structure consisting of B1, SW1, SW2, and AP1). Regarding claim 5, Nan teaches the circuit of claim 1, wherein the control input receives digital information pertaining to the current demand of the load (Page 7 Col.1; “digital control” using the comparators in Fig. 2). Regarding claim 6, Nan teaches the circuit of claim 1, wherein the control input receives control information related to the magnitude of the load current from a direct or indirect measurement of the load current (Page 7 Col. 1). Regarding claim 7, Nan teaches the circuit of claim 6, wherein the control information is generated using a current mirror (Fig. 4a shows the comparator circuit in detail which consists of a current mirror). Regarding claim 8, Nan teaches the circuit of claim 7, wherein the control information is a current and sets a bias in the variable current source (Page 7 col. 2 – Page 8 col. 1; Description for fig. 4a). Claim(s) 1-4 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US 20160056798 by Chan. Regarding claim 1, Chan teaches a buffer amplifier circuit (Fig. 2), comprising: a driver (Fig. 2 op amp #120 with transistors #225; Par. 19) that supplies current to a load in dependence on a voltage on the variable load (Fig. 2 Cload and I_Load); at least one variable current source Fig. 2 #100 and #110), the variable current source being arranged in use to supply current to the variable load; and a control input receiving control information pertaining to a current demand of the load (Par. 20); and wherein the at least one variable current source is controlled in dependence on the received control information to vary its output current such that current from the driver and the variable current source address the current requirements of the load, with at least a majority of the current requirements of the load being supplied by the variable current source (Par. 20). Regarding claim 2, Chan teaches the circuit of claim 1, wherein the driver (Fig. 2 #225) is the output stage of an operational amplifier (Par. 19). Regarding claim 3, Chan teaches the circuit of claim 1, wherein the driver (Fig. 2 #225) is separate from the at least one variable current source (Fig. 2 #100 and #110). Regarding claim 4, Chan teaches the circuit of claim 1, wherein all of the current requirements of the variable load are supplied by the variable current source (Par. 20 output current I_TAT is total current (I_Load+I_Bias drawn through the variable current source)). Allowable Subject Matter Claims 9-11 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Claims 13-20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NAREH SHAMIRYAN whose telephone number is (703)756-4616. The examiner can normally be reached M-F: 7:00AM-4:00PM PT. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren-Baltzell can be reached at (571) 272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NAREH SHAMIRYAN/Examiner, Art Unit 2843 /ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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Prosecution Timeline

Aug 02, 2023
Application Filed
Nov 24, 2025
Examiner Interview (Telephonic)
Nov 24, 2025
Examiner Interview Summary
Dec 09, 2025
Applicant Interview (Telephonic)
Jan 05, 2026
Non-Final Rejection — §102, §112
Mar 16, 2026
Response after Non-Final Action
Mar 16, 2026
Response Filed

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
95%
Grant Probability
99%
With Interview (+6.5%)
3y 2m
Median Time to Grant
Low
PTA Risk
Based on 43 resolved cases by this examiner. Grant probability derived from career allow rate.

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