DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is in response to Application 18/230387 filed on August 4, 2023 in which Claims 1-20 are presented for examination.
Status of Claims
Claims 1-20 are pending. Claims 1-5, 7-11, 13, 15-17 and 19 are rejected under 102. Claims 6, 12, 14, 18 and 20 are rejected under 103.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on October 29, 2024 was filed after the mailing date of the Application on August 4, 2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
The information disclosure statement (IDS) submitted on January 3, 2025 was filed after the mailing date of the Application on August 4, 2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
The information disclosure statement (IDS) submitted on August 13, 2026 was filed after the mailing date of the Application on August 4, 2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
The information disclosure statement (IDS) submitted on August 18, 2026 was filed after the mailing date of the Application on August 4, 2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5, 7-11, 13, 15-17 and 19 is/are rejected under 35 U.S.C. 102 as being anticipated by Cardona (US Patent Application 2015/0169416).
Claim 1, Cardona teaches an apparatus comprising: a first programmable network interface device comprising a network interface, a direct memory access (DMA) circuitry, a host interface, and at least one processor to execute a first process (View Cardona ¶ 21, 59, 60, 67; primary and standby adapters may be any network adapter, IO adapter, or the like, and may comprise an Ethernet adapter, iSCSI adapter, a Fibre Channel adapter, or the like. Thus, in some embodiments, the primary adapter and the standby adapter may comprise network adapters also termed NICs (network interface cards)) and a second programmable network interface device comprising a network interface, a DMA circuitry, a host interface, and at least one processor, wherein the at least one processor of the second programmable network interface device is to perform failover execution of the first process (View Cardona ¶ 20, 26, 59, 60, 67; when a connectivity failure error occurs between a primary adapter and a switch in a switch fabric, rather than having to tear down the connection, thereby losing state information, the illustrative embodiments may failover to a secondary standby adapter with the state and data being transferred from the primary adapter to the standby adapter. Hence state information in a stateful offload engine of the primary adapter is not lost when a connectivity failure occurs).
Claim 9 is the medium corresponding to the apparatus of Claim 1 and is therefore rejected under the same reasons set forth in the rejection of Claim 1.
Claim 15 is the method corresponding to the apparatus of Claim 1 and is therefore rejected under the same reasons set forth in the rejection of Claim 1.
Claim 2, most of the limitations of this claim have been noted in the rejection of Claim 1. Cardona further teaches a connection between the first programmable network interface device and the second programmable network interface device (View Cardona ¶ 58; the computer may include both a primary adapter and a secondary or standby adapter, and may further include an input-output (IO) bus 365 and an IO bus 390. IO bus 365 and IO bus 390 may be redundant buses, primary and secondary buses, parallel buses, or different types of buses with distinct, primary functions. In one illustrative embodiment, IO bus 365 and IO bus 390 both connect to the primary adapter and standby adapter to facilitate failover), wherein the first programmable network interface device is to provide state of the first process for failover execution of the first process on the at least one processor of the programmable second network interface device (View Cardona ¶ 18, 19, 26; the state and connection information for the connections being serviced by the primary adapter is not lost and instead is copied to the standby adapter).
Claim 3, most of the limitations of this claim have been noted in the rejection of Claim 2. Cardona further teaches the connection comprises a switch and/or the host interface of the first programmable network interface device and the host interface of the second programmable network interface device (View Cardona ¶ 3, 26, 57; failover system may comprise a computer having a primary adapter and a secondary or standby adapter which are coupled to a network comprising a switch fabric).
Claim 4, most of the limitations of this claim have been noted in the rejection of Claim 1. Cardona further teaches the at least one processor of the second programmable network interface device is to perform failover execution of the first process based on degradation of performance of the first process as executed by the at least one processor of the first programmable network interface device (View Cardona ¶ 73; imminent failure of the primary adapter may be detected by monitoring various performance characteristics of the primary adapter and determining if changes in the performance characteristics are indicative of an imminent failure; performance characteristic may be any characteristic indicative of the primary adapter’s ability to handle communication data processing over one or more communication links through the primary adapter, e.g., link health characteristics, data flow rates, error bits, dropped packets, or the like).
Claim 10 is the medium corresponding to the apparatus of Claim 4 and is therefore rejected under the same reasons set forth in the rejection of Claim 4.
Claim 16 is the method corresponding to the apparatus of Claim 4 and is therefore rejected under the same reasons set forth in the rejection of Claim 4.
Claim 5, most of the limitations of this claim have been noted in the rejection of Claim 1. Cardona further teaches the at least one processor of the second programmable network interface device is to copy state of the first process as executed by the at least one processor of the first programmable network interface device (View Cardona ¶ 76, 78; detecting the imminent failure of the primary adapter, and the sending of the initiate failover message to the secondary adapter, information required to construct a consistent view of the ingress DMA queue and egress DMA queue of the primary adapter on the secondary adapter is copied over to the secondary adapter by the failover logic of the primary adapter; information that is copied over may include, among other data, the address and depths of each DMA queue, Quality of Service (QoS) attributes, state/connection tables, offload options, virtualization options and tables, statistics, and the like) and the at least one processor of the second programmable network interface device is to perform failover execution of the first process based on the copied state (View Cardona ¶ 76, 78; information copied over to the secondary adapter is used by the failover logic of the secondary adapter to set up the secondary adapter's local resources, e.g., local ingress buffer and egress buffer for access to ingress DMA queue 323 and egress DMA queue in host memory, as well as any other necessary resources for taking over the operation of the primary adapter. These resources are configured to mirror the resources of the primary adapte0 such that the resources on the secondary adapter utilize similar address, depths, QoS parameters, and the like and are able to step in for the primary adapter in response to notifying the host system that the failover operation has been completed).
Claim 11 is the medium corresponding to the apparatus of Claim 5 and is therefore rejected under the same reasons set forth in the rejection of Claim 5.
Claim 17 is the method corresponding to the apparatus of Claim 5 and is therefore rejected under the same reasons set forth in the rejection of Claim 5.
Claim 7, most of the limitations of this claim have been noted in the rejection of Claim 5. Cardona further teaches the at least one processor of the first programmable network interface device to execute the first process comprises one or more of: a central processing unit (CPU), a graphics processing unit (GPU), or an accelerator (View Cardona ¶ 40, 47, 50; operating system runs on processing unit. The operating system coordinates and provides control of various components within the data processing system; computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks) and the at least one processor of the second programmable network interface device to perform failover execution of the first process based on the copied state comprises one or more of: a CPU, a GPU, or an accelerator (View Cardona ¶ 40, 47, 50, 56; operating system runs on processing unit. The operating system coordinates and provides control of various components within the data processing system; one or more of the computing devices in FIG. 1, e.g., servers 104, 106 or clients 110-114, comprise network adapters implementing hardware/software logic for performing failover operations for failing over from a primary adapter to a secondary or standby adapter in the case of an imminent failure of the primary adapter being detected).
Claim 8, most of the limitations of this claim have been noted in the rejection of Claim 1. Cardona further teaches the at least one processor of the second programmable network interface device is to cause the host interface of the second programmable network interface device to output data, generated by the first process executed by the at least one processor of the second programmable network interface device, to a host platform (View Cardona ¶ 22, 24; ingress data is received over the failover adapter and written to the host memory while egress data continues to be transmitted from the host system via the primary adapter).
Claim 13 is the medium corresponding to the apparatus of Claim 8 and is therefore rejected under the same reasons set forth in the rejection of Claim 8.
Claim 19 is the method corresponding to the apparatus of Claim 8 and is therefore rejected under the same reasons set forth in the rejection of Claim 8.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6, 12 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cardona (US Patent Application 2015/0169416) in view of Lacey (US Patent Application 2022/0164255).
Claim 6, most of the limitations of this claim have been noted in the rejection of Claim 5. Cardona does not explicitly teach the copied state comprises one or more of: contents of registers, program counter content, operating system (OS) specific data, condition registers, or packet header and/or data.
However, Lacey teaches the copied state comprises one or more of: contents of registers, program counter content, operating system (OS) specific data, condition registers, or packet header and/or data (View Lacey ¶ 12, 45; recording in a memory of the first subsystem i) a respective program state of the second program, comprising at least a state of one or more registers on each of the second processors at the time of the respective checkpoint, and ii) a copy of the data content sent to the second subsystem in the time since the respective checkpoint).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to modify Cardona with the copied state comprises one or more of: contents of registers, program counter content, operating system (OS) specific data, condition registers, or packet header and/or data since it is known in the art that a checkpoint can include data to be failed over (View Lacey ¶ 12, 45). Such modification would have allowed system information to be failed over.
Claim 12 is the medium corresponding to the apparatus of Claim 6 and is therefore rejected under the same reasons set forth in the rejection of Claim 6.
Claim 18 is the method corresponding to the apparatus of Claim 6 and is therefore rejected under the same reasons set forth in the rejection of Claim 6.
Claim(s) 14 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cardona (US Patent Application 2015/0169416) in view of Patankar (US Patent Application 2012/0005164).
Claim 14, most of the limitations of this claim have been noted in the rejection of Claim 9. Cardona does not explicitly teach to perform failover execution of a first process, the at least one processor of the second programmable network interface device is to restart execution of the first process.
However, Patankar teaches to perform failover execution of a first process, the at least one processor of the second programmable network interface device is to restart execution of the first process (View Patankar ¶ 5; “switching over" primary application execution to another resource, HA clustering usually attempts to provide "restart" or "continuation" of primary application operations on the other system without requiring administrative intervention (e.g., a process known as Failover, etc.)).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to modify Cardona with to perform failover execution of a first process, the at least one processor of the second programmable network interface device is to restart execution of the first process since it is known in the art that a process can be restarted (View Patankar ¶ 5). Such modification would have allowed a process to be restarted after a failover.
Claim 20 is the method corresponding to the apparatus of Claim 14 and is therefore rejected under the same reasons set forth in the rejection of Claim 14.
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure:
Allen et al. (U.S. Patent Application 2016/0062854); teaches availability can be implemented through redundant software and/or hardware, which takes over the functionality in the event a component failure is detected. In order to succeed, the failover replicates not only the data, but also the process state.
Sisterhen et al. (U.S. Patent Application 2021/0349842); teaches a network driver (e.g., program instructions stored in memory and executable by a processor and/or processing circuitry) of a first (computer) system may be configured to provide a virtual network connection to a second (computer) system. In some embodiments, the first system and the second system may operate based on differing processor architectures and the virtual network connection may be via programmable hardware (e.g., such as a field programmable gate array (FPGA) fabric) in communication via bus interfaces with the first and second systems.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARAI E BUTLER whose telephone number is (571)270-3823. The examiner can normally be reached 8 am to 4 pm.
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/SARAI E BUTLER/Primary Examiner, Art Unit 2114
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