DETAILED ACTION
This office action is in response to Application No. 18/230,405, filed on 4 August 2023. Claims 1-20 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1, 3-5, and 7-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 4-16, and 19 of U.S. Patent No. 11,755,806. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of patent recite or encompass all of the limitations of the application’s claims. Claims 1-5 and 7-17 are alternatively rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-14 of U.S. Patent No. 11,755,806 in view of Wilder (US 2010/0274990).
Independent claim 1 corresponds to claim 1 of the patent, but omits terms and limitations (fetchless, identifying initialization parameters) and rewords other limitations (initializing programmable FSM -> programming a FSM). Claim 1 also recites additional limitations that are not explicitly present in patented claim 1, but are strongly implied or inherent: “at runtime, executing the FSM based on a start signal” is necessarily present in the patented claim, since whatever signal causes execution of the FSM would be considered the start signal; and “transmission of the plurality of control signals to the computational circuit” is necessarily present in the patented claim, because the FSM controls operation of the computational circuit by transmitting the control signals. Claim 1 of the patent otherwise recites all of the limitations of claim 1 of the application essentially verbatim, and thus encompasses all of the subject matter of claim 1.
If patented claim 1 is found to be unclear regarding the start signal and the transmission of control signals to the computational circuit, Wilder discloses the same (¶97). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine patented claim 1 with the teachings of Wilder, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of initiating and controlling operation of a computational circuit using the FSM that is programmed to initiate and control operations of the computational circuit. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Patented claim 1 recites an FSM that controls executing of a computational loop on a computational circuit through transmitting control signals. As discussed above, persons having ordinary skill in the art would recognize that the FSM would necessarily begin operation based on some sort of start signal and control operation of the computational circuit by transmitting control signals to the computational circuit, as taught by Wilder. The teachings of Wilder are directly applicable to patented claim 1, so that the claimed FSM would similarly begin operation in response to the necessary start signal and control operation of the computational circuit through transmission of control signals to the computational circuit, such that the FSM could function as claimed.
Independent claim 18 corresponds to claim 14 of the patent, and omits or rewords limitations in the same way as claim 1. Claim 14 of the patent otherwise recites all of the limitations of claim 18 of the application essentially verbatim, and thus encompasses all of the subject matter of claim 18.
Independent claim 20 corresponds to claim 18 of the patent, but omits terms and limitations (programmable, identifying programming instructions) and rewords other limitations (operations -> computations; programming -> encoding, initialization -> configuring). Claim 18 of the patent otherwise recites all of the limitations of claim 20 of the application essentially verbatim, and thus encompasses all of the subject matter of claim 18.
Claim 2 corresponds to claims 12 and/or 13 of the patent. Although the patented claims do not explicitly recite that “the FSM is controllably connected to a plurality of processing cores, each of the plurality of processing cores having at least one computational circuit”, as recited in claim 2, patent claims 12 and 13 both recite the FSM issuing control signals to multiple processing elements such as multiply-accumulate circuits, which are computational circuits. Computational circuits are also inherent to “processing cores”, since the function of processing cores is to perform processing, i.e. computations.
Claims 3 and 5 correspond to claim 1 of the patent. Patented claim 1 requires “fetchless” computations, and so excludes fetches of computational loop instructions or data movement instructions.
Claims 4 and 7-17, and 19 correspond to patented claims 2, 3-13, and 16, respectively, and recite substantially identical limitations.
Claim 6 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 2 of U.S. Patent No. 11,755,806 in view of Ware (US 2022/0283779), or in the alternative, in view of Wilder and Ware.
Regarding claim 6, patented claim 2 does not explicitly recite that the register file is associated with one or more data output ports of the first processing core and data input ports of the first processing core, wherein the data input ports of the first processing core are directly connected to data output ports of the neighboring processing cores; and executing the at least one data movement instruction causes the input data to rotate an angle from the data input ports of the first processing core to the one or more data output ports of the first processing core. However, patented claim 2 recites that the data movement instruction moves input data from a register file of a processing core to data input ports of neighboring processing cores, which implies or requires that the register file is associated with one or more data output ports of the first processing core and data input ports of the first processing core, wherein the data input ports of the first processing core are directly connected to data output ports of the neighboring processing cores, since the input data in the register is being output from one processing core to a neighboring processing core.
Ware also discloses the register file is associated with one or more data output ports of the first processing core and data input ports of the first processing core, wherein the data input ports of the first processing core are directly connected to data output ports of the neighboring processing cores; and executing the at least one data movement instruction causes the input data to rotate an angle from the data input ports of the first processing core to the one or more data output ports of the first processing core (¶¶5, 7, 21). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine patented claim 2 with the teachings of Ware, because doing so would have involved merely the routine combination of known elements according to known techniques, or the substitution of an element for a known equivalent, to produce merely the predictable results of correctly computing convolutions using a MAC pipeline. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Patented claim 2 recites controlling a plurality of processing cores to perform repeated operations. Ware teaches performing repeated operations with the cores, where the input data is moved between cores. The teachings of Ware are directly applicable to patented claim 2 in the same way, so that input data would similarly be moved between processing cores to perform operations
As discussed above, parent claim 1 is obvious over claim 1 of the patent, or alternatively over patented claim 1 in view of Wilder. Similarly, dependent claim 6 is obvious over patented claim 1 in view of Ware, or patented claim 1 in view of Wilder and Ware, under the same reasoning.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 16, and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wilder (US 2010/0274990).
Regarding claim 1, Wilder discloses a method for accelerating an execution of computational loops on an integrated circuit (¶44), the method comprising: programming a finite state machine (FSM) based on a loop iteration parameter comprising a number of computation cycles of a computational loop to be executed by a computational circuit (¶18);
at runtime, executing the FSM based on a start signal, wherein executing the FSM includes: (i) generating, by the FSM, a plurality of control signals including a distinct control signal for each of the number of computation cycles of the computational loop; and (ii) controlling, by the FSM, an operation of the computational circuit executing the computational loop based on a transmission of the plurality of control signals to the computational circuit (¶¶18, 97).
Regarding claim 2, Wilder discloses that the FSM is controllably connected to a plurality of processing cores, each of the plurality of processing cores having at least one computational circuit (¶44).
Regarding claim 3, Wilder discloses that at runtime, the FSM is executed without performing fetches of computational loop instructions (¶16).
Regarding claim 16, Wilder discloses that at runtime, the FSM generates the plurality of controls signals causing an execution of an N-way multiply accumulate with computation weights and computation input data, wherein: N relates to a number of distinct multiply accumulate circuits concurrently executing a distinct computational loop, and N is greater than one (¶¶14, 65).
Regarding claim 18, Wilder discloses a method comprising: programming a finite state machine (FSM) based on one or more FSM initialization parameters, wherein the one or more FSM initialization parameters include a loop iteration parameter comprising a number of multiply-accumulate computation cycles of a convolutional loop (¶¶14, 17);
at runtime, implementing the FSM to enable one or more computations by: (i) generating, by the FSM, a plurality of convolutional loop control signals based on the loop iteration parameter; and (ii) controlling, by the FSM, an execution of a plurality of multiply-accumulate computation cycles of a multiply accumulator circuit (MAC) performing the convolutional loop based on transmitting the plurality of convolutional loop control signals until the number of multiply-accumulate computation cycles of the convolutional loop are completed (¶¶14, 17, 97, 98).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-7, 9, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wilder in view of Ware (US 2022/0283779).
Regarding claim 4, Wilder does not appear to explicitly disclose programming the FSM based on a data movement parameter comprising at least one data movement instruction that, when executed, moves input data from a register file of a first processing core to data input ports of neighboring processing cores. Ware discloses these limitations (¶¶5, 7). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Wilder and Ware, because doing so would have involved merely the routine combination of known elements according to known techniques, or the substitution of an element for a known equivalent, to produce merely the predictable results of correctly computing convolutions using a MAC pipeline. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Wilder discloses controlling a plurality of MAC units to perform repeated MAC computations. Ware teaches performing convolutions with repeated MAC computations, where the input data is moved between MAC units. The teachings of Ware are directly applicable to Wilder in the same way, so that Wilder would similarly move input data between MAC units to perform convolution operations using the MAC units.
Regarding claim 5, Wilder discloses that at runtime, the FSM is executed without performing fetches of data movement instructions (¶16).
Regarding claim 6, Wilder does not appear to explicitly disclose that the register file is associated with one or more data output ports of the first processing core and data input ports of the first processing core, wherein the data input ports of the first processing core are directly connected to data output ports of the neighboring processing cores; and executing the at least one data movement instruction causes the input data to rotate an angle from the data input ports of the first processing core to the one or more data output ports of the first processing core. Ware discloses these limitations (¶¶5, 7, 21). Motivation to combine remains consistent with claim 4.
Regarding claim 7, Wilder discloses that at runtime, executing the FSM causes an execution of the computational loop based on the loop iteration parameter (¶¶18, 97), but does not appear to explicitly disclose subsequently, executing the FSM causes an execution of one or more computational loops based on the loop iteration parameter and the data movement parameter. Ware discloses executing the FSM causes an execution of one or more computational loops based on the loop iteration parameter and the data movement parameter (¶¶4, 7, 12). Motivation to combine remains consistent with claim 4.
Regarding claim 9, Wilder does not appear to explicitly disclose that programming the FSM includes identifying, by the FSM, a distinct data movement control signal for each of the number of computation cycles of the computational loop based on the loop iteration parameter and a data movement parameter. Ware discloses these limitations (¶21). Motivation to combine remains consistent with claim 4.
Regarding claim 10, Wilder does not appear to explicitly disclose that controlling the operation of the computational circuit executing the computational loop includes transmitting, by the FSM, the distinct data movement control signal for each of the number of computation cycles of the computational loop until the number of computation cycles of the computational loop are completed. Ware discloses these limitations (¶21). Motivation to combine remains consistent with claim 4.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wilder in view of Ware and Li (US 2018/0267809).
Regarding claim 8, Wilder discloses that at runtime, the FSM generates: a first set of control signals of the plurality of control signals for executing the computational loop based on the loop iteration parameter; and, a second set of control signals of the plurality of control signals for executing (a) the number of computation cycles of the computational loop (¶18). Wilder does not appear to explicitly disclose the second set of control signals of the plurality of control signals for executing (a) the number of computation cycles of the computational loop and (b) the at least one data movement instruction based on the loop iteration parameter and the data movement parameter; Ware discloses these limitations (¶¶4, 7, 12, 21). Motivation to combine remains consistent with claim 4.
Wilder does not appear to explicitly disclose that the generation of the second set of control signals is in response to completing the computational loop based on the loop iteration parameter; Li discloses these limitations (¶138). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Wilder, Ware, and Li, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of executing multiple instructions. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Wilder discloses controlling execution of a repeated computation instruction. Ware teaches data movement instructions to control data flow between processing elements when executing computations. Li teaches that after completing execution of a repeated computation instruction, the processing elements execute subsequent repeated computation instructions. The teachings of Li are directly applicable to Wilder, so that Wilder would similarly execute subsequent repeated computation instructions after execution of a repeated computation is complete, in order to execute multiple repeated computation instructions.
Claim(s) 11-13 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wilder in view of Hou (US 2021/0240483).
Regarding claim 11, Wilder does not appear to explicitly disclose that programming the FSM includes encoding a starting memory address parameter to a start memory address register file accessible to one or more computational circuits controllable by the FSM. Hou discloses these limitations (Fig. 1; ¶22). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Wilder and Hou, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of retrieving operands from memory. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Wilder discloses computing matrix operations by controlling processing cores comprising MACs. Hou teaches encoding starting memory address and filter size parameters so that the correct matrix operands for the computations are retrieved by the MACs. The teachings of Hou are directly applicable to Wilder in the same way, so that Wilder would similarly encode starting memory address and filter sizes to retrieve the correct operands from memory for MAC operation.
Regarding claim 12, Wilder does not appear to explicitly disclose that the starting memory address parameter comprises a register file pointer that points to a head of input data at a location within an n-dimensional memory stored within at least one processing core controllable by the FSM. Hou discloses these limitations (Fig. 1; ¶31). Motivation to combine remains consistent with claim 11.
Regarding claim 13, Wilder does not appear to explicitly disclose that programming the FSM includes encoding a convolution filter size parameter to a convolution register file of at least one processing core controllable by the FSM. Hou discloses these limitations (Fig. 1; ¶22). Motivation to combine remains consistent with claim 11.
Regarding claim 19, Wilder discloses that programming the FSM includes programming one or more iteration parameters at one or more iteration register files accessible to the FSM (¶95), but does not appear to explicitly disclose (i) programming a starting memory address parameter at a start memory address register file accessible to the MAC; (ii) programming a convolution filter size parameter at a convolution register file accessible to the MAC. Hou discloses these limitations (Fig. 1; ¶22). Motivation to combine remains consistent with claim 11.
Claim(s) 14 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wilder in view of Hou and Henry (US 2018/0276035).
Regarding claim 14, Wilder does not appear to explicitly disclose that the convolution filter size parameter comprises a value that maps to one of a plurality of distinct convolutional filter sizes for a given convolutional computation by a multiply accumulator circuit of the at least one processing core. Hou discloses these limitations (¶22). If Hou is found to be unclear regarding these limitations, Henry discloses the same (¶222). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Wilder, Hou, and Henry, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of retrieving filter values from memory according to conventional filter sizes. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Wilder teaches controlling convolution operations. As discussed above with regard to claim 11, Hou teaches encoding filter size to correctly retrieve filter values from memory for convolution operations. Persons having ordinary skill in the art, reading Hou, would understand that defining the size of the filter in terms of row and column dimensions necessarily maps to distinct convolution filter sizes, as taught by Henry. The teachings of Hou and Henry are directly applicable to Wilder, so that Wilder would similarly define distinct filter dimensions to correctly retrieve filter values from memory.
Regarding claim 17, Wilder discloses that if a convolution filter size parameter of the FSM includes a value that maps to one of a plurality of distinct convolutional filter sizes that is greater than a 1x1 convolutional filter size, the FSM broadcasts input data pointed to by a starting memory address parameter to a collection of processing cores in neighboring proximity to the FSM (¶¶15, 78, 86). If Wilder is found to be unclear regarding the filter size parameter and starting memory address parameter, Hou discloses the same (¶22). If Wilder is found to be unclear regarding the plurality of distinct convolutional filter sizes, Henry discloses the same (¶222). Motivation to combine remains consistent with claim 14.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wilder in view of Li.
Regarding claim 15, Wilder does not appear to explicitly disclose that programming the FSM includes encoding the loop iteration parameter to a combination of distinct iteration register files of at least one processing core controllable by the FSM. Li discloses these limitations (claim 5; ¶¶8, 128). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Wilder and Li, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of independently configuring and controlling processing elements. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Wilder discloses performing computations using a plurality of processing elements. Li teaches that each processing element receives configuration data for performing the computations. The teachings of Li are directly applicable to Wilder the same way, so that Wilder’s processing elements would similarly receive configuration data to allow independent control of the processing elements.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wilder in view of Ware and Hou.
Regarding claim 20, Wilder discloses a method for implementing finite state machine (FSM)-controlled convolutional computations on an integrated circuit (¶¶18, 44), the method comprising: configuring an FSM based on one or more FSM programming instructions, wherein the FSM controls: (a) computations of multiply accumulator circuits (MACs) of a plurality of distinct processing cores (¶44);
wherein configuring the FSM includes: (3) encoding an iteration value to at least one iteration register file associated with the FSM, wherein the iteration value identifies a number of cycles of a convolutional loop performed by at least one of the MACs (¶¶18, 95); and executing a Boolean switch based on the configuring of the FSM that starts an operation of the FSM for generating control signals to the MACs for automatically executing one or more distinct convolutional loops (¶¶18, 97).
Wilder does not appear to explicitly disclose data movement operations of data ports of the plurality of distinct processing cores. Ware discloses a method for implementing finite state machine (FSM)-controlled convolutional computations on an integrated circuit (¶¶12, 18), the method comprising: configuring an FSM based on one or more FSM programming instructions, wherein the FSM controls: (b) data movement operations of data ports of the plurality of distinct processing cores (¶7). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Wilder and Ware, because doing so would have involved merely the routine combination of known elements according to known techniques, or the substitution of an element for a known equivalent, to produce merely the predictable results of correctly computing convolutions using a MAC pipeline. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Wilder discloses controlling a plurality of MAC units to perform repeated MAC computations. Ware teaches performing convolutions with repeated MAC computations, where the input data is moved between MAC units. The teachings of Ware are directly applicable to Wilder in the same way, so that Wilder would similarly move input data between MAC units to perform convolution operations using the MAC units.
Wilder does not appear to explicitly disclose (1) encoding a starting memory address value to an address register file accessible to the MACs of the plurality of distinct processing cores, and (2) encoding a convolutional filter size to a convolutional register file associated with the FSM. Hou discloses these limitations (Fig. 1; ¶22). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Wilder, Ware, and Hou, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of retrieving operands from memory. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Wilder discloses computing matrix operations by controlling processing cores comprising MACs. Hou teaches encoding starting memory address and filter size parameters so that the correct matrix operands for the computations are retrieved by the MACs. The teachings of Hou are directly applicable to Wilder in the same way, so that Wilder would similarly encode starting memory address and filter sizes to retrieve the correct operands from memory for MAC operation.
Conclusion
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22 December 2025
/ARIC LIN/ Examiner, Art Unit 2851