DETAILED ACTION
1. This office action is in response to the Application No. 18230912 filed on 05/09/2026. Claims 1-20 are presented for examination and are currently pending. Applicant’s arguments have been carefully and respectfully considered.
Response to Arguments
2. The Applicant’s argument on pages 10-11 that “The recited combination of "a data order memory configured to store data-address order information, the data-address order information representing an order of memory addresses for an artificial neural network data operation," "at least one buffer memory configured to cache data of the artificial neural network data operation," and the ordered operations of predicting a second memory read request by referring to the data- address order information, caching the corresponding data, determining whether the prediction matches the actual subsequent request from the processor, and providing the cached data, addresses the processor-memory latency bottleneck that is recognized in the specification as the dominant performance limit for data-intensive artificial neural network operations (see, e.g., the specification, [0016], and [0022]-[0026])” and “However, these limitations, when combined, advantageously create a memory subsystem that anticipates and serves the processor's next data request during an artificial neural network operation without incurring the access latency that would otherwise stall the processor (see, e.g., the specification, [0016], [0022]-[0026] and [0029])” are persuasive because it improves the functioning of the computer. As a result, the 101 rejection has been withdrawn.
The Applicants argument regarding the prior art has been considered and the
Examiner is withdrawing the rejections in the previous Office action because Applicant’s
amendment necessitated new grounds of rejection presented in this Office Action. It is
noted that arguments regarding independent claims 1 and 20 has been considered but
are moot because a new references has now been used to remap the independent
claims 1 and 20.
However, on page 16 of the remarks, the Applicant argued that “Independent claim 11 further recites "control at least one memory storing data corresponding to the second memory read request to maintain a ready state in which the second memory read request can be executed." None of the cited references discloses, teaches, or suggests controlling at least one memory to maintain a ready state based on a memory read request that is predicted by referring to data-address order information representing an order of memory addresses for an artificial neural network data operation”.
It is noted that a new secondary reference has been applied to teach the amended limitation “the data- address order information representing an order of memory addresses for an artificial neural network data operation”.
Furthermore, Dropps still teaches control at least one memory storing a data corresponding to the second memory read request to maintain a ready state in which the second memory read request can be executed (... the node controller 110 to execute a request to retrieve (e.g., pre-fetch) a predicted data block, such as a read request ... for the data, from the remote memory 120 before one of the processor nodes issues the request [0012]). The Applicant has not provided any argument why Dropps does not teach the limitation “control at least one memory storing a data corresponding to the second memory read request to maintain a ready state in which the second memory read request can be executed”. As a result, Dropps is still applied to teach the above limitation.
In addition, Nelogal in view of Dropps in view of Luo has now been applied to teach the limitations of claim 11.
It is noted that Shirota which was applied in the previous Office Action is still
relevant to the instant dependent claims. As a result, their teachings have been used in this Office Action. The dependent claims 2-10 and 12-19 which depend directly or
indirectly from independent claims 1 and 11 are not patentable because the instant
claims are still obvious over the prior art of record
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1-5, 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Nelogal et al. (US20200285386 filed 03/07/2019) in view of Loh (US20200183848 filed 12/10/2018) and further in view of Luo et al. (US20200034306 filed 07/24/2018)
Regarding claim 1, Nelogal teaches a data management device (The network resource can include ... a data storage system [0017]), comprising:
configured to cache data of an artificial neural network data operation (As an example, the output of the predictive subsystem may be provided as an input to layers such as a cache manager, which may manage a caching implementation. The cache manager may provide measured input on the success of the predictive model (e.g., hit/miss ratios) of the pre-fetched pages to the LSTM subsystem [0030]); and
wherein the data management device is configured to: receive a first memory read request from a processor (At block 203, information characteristic of data being transferred is obtained. As an example, a type of I/O request (e.g., read or write), a starting logical block address (LBA) of the request, a size of I/O data transferred according to the request, and a inter-LBA distance between I/O requests can be obtained [0018]; ... carrying a set of instructions for execution by a processor [0035]);
predict a second memory read request to be requested following the first memory read request (Predictive subsystem 151 utilizes a neural network, such as a recursive neural network (RNN), to perform deep learning of I/O patterns and to create a model to predict upcoming I/O requests [0015]) by referring to the data-address order information (As an example, latency information as to durations over which I/O requests are completed and counts of numbers of I/O requests in a pertinent LBA address range are obtained [0018]);
cache a data corresponding to the second memory read request from at least one memory to the at least one buffer memory (In accordance with at least one embodiment, I/O parameters for which I/O parameter values can be provided to the predictive subsystem include ... cache LBA hit/miss information [0032]);
Nelogal does not explicitly teach a data order memory configured to store data-address order information, the data-address order information representing an order of memory addresses for an artificial neural network data operation; and at least one buffer memory; and provide the data corresponding to the second memory read request cached in the at least one buffer memory to the processor.
Loh teaches a data order memory configured to store data-address order information (The first address 154 is a copy of the address 122, which points to a memory location storing data at the beginning of the region 120. The second address 156 is a copy of the address 142, which points to a memory location storing data at the beginning of the region 140 ... For example, the region parameters 150 currently stores a memory mapping between the address 122 (“x”) and the address 142 (“a”) [0035]); and
at least one buffer memory configured to cache data (... in some designs, the in-package cache 330 uses multiple memory arrays 332 that are segmented into multiple banks. In such cases, each one of the banks includes a respective row buffer [0048]);
of an artificial neural network data operation (From points in time t1 to 11t7 (or times t1 to t7), the size and content of the region stored in the last-level cache 1130 changes. The data 1120 corresponds to a first layer of weights of a multi-layer neural network. The data 1122 corresponds to a second layer of weights of the multi-layer neural network, and so on [0078]);
and provide the data corresponding to the second memory read request cached in the at least one buffer memory to the processor (Each one of the row buffers stores data in an accessed row of the multiple rows within the corresponding memory array bank [0048]; Again, the processing unit 420 is ... data processing device that makes use of a row-based memory, such as a cache [0058]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Nelogal to incorporate the teachings of Loh for the benefit of improving data transfer rates between these units while reducing power consumption (Loh [0044])
Nelogal and Loh does not explicitly teach a data order memory configured to store data-address order information, the data-address order information representing an order of memory addresses for an artificial neural network data operation; determine whether the second memory read request and a third memory read request generated by the processor are a same;
Luo teaches a data order memory configured to store data-address order information (The generated sequence of addresses may provide a different form of address identification for data stored in the memory units 140 a/140 b, such that data may be retrieved from the memory units 140 a/140 b according to the generated sequence of addresses [0022]),
the data-address order information representing an order of memory addresses for an artificial neural network data operation (sequences of addresses generated for certain memory operations, as described herein, may be generated according to a particular pattern which may facilitate tensor operations [0014]; Tensors, which are generally geometric objects related to a linear system, may be utilized in machine learning and artificial intelligence applications [0002]);
determine whether the second memory read request and a third memory read request generated by the processor are a same ( the data address generator 520 may determine for subsequent memory commands whether a memory command is requesting the same information that was stored at the first sequence of memory addresses [0048]. The Examiner notes that subsequent memory commands includes second memory read requests and a third memory read request);
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Nelogal and Loh to incorporate the teachings of Luo for the benefit of high speed memory access, and reduced power consumption (Luo [0001])
Regarding claim 2, Nelogal, Loh and Luo teaches the data management device of claim 1, Loh teaches further comprising: a read/write address generator module configured to generate the data-address order information (In one example, the region 620 uses the address space 2,000 to 2,700 where the addresses are expressed as digits. The entire last-level cache 130 uses the address space 5,000 to 6,000 where the addresses are also expressed as digits [0065]; For example, in some designs, a first queue stores memory read requests and a second queue stores memory write requests. Logic within the cache controller selects a queue of the one or more queues and selects a memory access request from the selected queue. The logic determines a range of addresses corresponding to a first region of contiguous data stored in system memory [0026]).
The same motivation to combine independent claim 1 applies here.
Regarding claim 3, Nelogal, Loh and Luo teaches the data management device of claim 1, Loh teaches wherein the first memory read request is an artificial neural network data operation request (The accessing of the neural network's weights proceeds in a regular, predictable manner. Therefore, the region in the last-level cache 1130 is increased sufficiently ahead of the evaluation of the weights [0080]; For each memory access of the last-level cache 1330, logic compares the requested address against each valid, supported region in the last-level cache 1330 [0086]).
The same motivation to combine independent claim 1 applies here.
Regarding claim 4, Nelogal, Loh and Luo teaches the data management device of claim 1, Luo teaches wherein the data-address order information identifies, in advance, in advance an address of data required for a next artificial neural network data operation (For example, the memory controller 110 may identify, in the subsequently received memory command, a starting address that is also associated with the sequence of memory addresses [0038]).
The same motivation to combine independent claim 1 applies here.
Regarding claim 5, Nelogal, Loh and Luo teaches the data management device of claim 1, Loh teaches wherein the processor is one of a central processing unit (CPU), a graphics processing unit (GPU), a neural network processor (NNP), and a customized processor for artificial neural network data operation (Examples of a processing unit are a processor core within a general-purpose central processing unit (CPU), a graphics processing unit (GPU), or other ... One example of such a memory is a 3D integrated memory, such as a 3D DRAM [0040]; In one design example, the weights of a large (deep) neural network are stored in system memory 1110, such as off-package DRAM [0078]).
The same motivation to combine independent claim 1 applies here.
Regarding claim 10, Nelogal, Loh and Luo teaches the data management device of claim 1, Loh teaches wherein a memory area for input data, a memory area for weights, and a memory area for feature maps are allocated to the at least one memory (Data 1120-1128 are contiguous data stored in the system memory 1110 [0077]; As used herein, “contiguous data” refers to one or more bits of data located next to one another in data storage [0026]; In one design example, the weights of a large (deep) neural network are stored in system memory 1110, such as off-package DRAM [0078]).
The same motivation to combine independent claim 1 applies here.
Regarding claim 20, claim 20 is similar to claim 1. It is rejected in the same manner and reasoning applying. Further, Nelogal teaches an apparatus (In accordance with at least one embodiment, a method and apparatus are provided to predict and optimize a data storage subsystem [0027])
4. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Nelogal et al. (US20200285386 filed 03/07/2019) in view of Dropps (US20190114275 filed 10/17/2017) and further in view of Luo et al. (US20200034306 filed 07/24/2018)
Regarding claim 11, Nelogal teaches a data management device (The network resource can include ... a data storage system [0017]), comprising:
wherein the data management device is configured to: receive a first memory read request from a processor (At block 203, information characteristic of data being transferred is obtained. As an example, a type of I/O request (e.g., read or write), a starting logical block address (LBA) of the request, a size of I/O data transferred according to the request, and a inter-LBA distance between I/O requests can be obtained [0018]; ... carrying a set of instructions for execution by a processor [0035]);
predict a second memory read request to be requested following the first memory read request (Predictive subsystem 151 utilizes a neural network, such as a recursive neural network (RNN), to perform deep learning of I/O patterns and to create a model to predict upcoming I/O requests [0015]) by referring to the data-address order information (As an example, latency information as to durations over which I/O requests are completed and counts of numbers of I/O requests in a pertinent LBA address range are obtained [0018]); and
Nelogal does not explicitly teach a data order memory configured to store data-address order information; the data-address order information representing an order of memory addresses for an artificial neural network data operation; control at least one memory storing a data corresponding to the second memory read request to maintain a ready state in which the second memory read request can be executed.
Dropps teaches control at least one memory storing a data corresponding to the second memory read request to maintain a ready state in which the second memory read request can be executed (... the node controller 110 to execute a request to retrieve (e.g., pre-fetch) a predicted data block, such as a read request ... for the data, from the remote memory 120 before one of the processor nodes issues the request [0012]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Nelogal and Loh to incorporate the teachings of Dropps in order to save time for the processor nodes in having to access the remote memory themselves and increases the efficiency of access to the remote memory since processor node hand shaking to the node controller when accessing the remote memory can be reduced (Dropps [0012])
Nelogal and Dropps does not explicitly teach a data order memory configured to store data-address order information; the data-address order information representing an order of memory addresses for an artificial neural network data operation;
Luo teaches a data order memory configured to store data-address order information (The generated sequence of addresses may provide a different form of address identification for data stored in the memory units 140 a/140 b, such that data may be retrieved from the memory units 140 a/140 b according to the generated sequence of addresses [0022]),
the data-address order information representing an order of memory addresses for an artificial neural network data operation (sequences of addresses generated for certain memory operations, as described herein, may be generated according to a particular pattern which may facilitate tensor operations [0014]; Tensors, which are generally geometric objects related to a linear system, may be utilized in machine learning and artificial intelligence applications [0002]);
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Nelogal and Dropps to incorporate the teachings of Luo for the benefit of high speed memory access, and reduced power consumption (Luo [0001])
5. Claims 12-19 and are rejected under 35 U.S.C. 103 as being unpatentable over Nelogal et al. (US20200285386 filed 03/07/2019) in view of Dropps (US20190114275 filed 10/17/2017) in view of Luo et al. (US20200034306 filed 07/24/2018) and further in view of Loh (US20200183848 filed 12/10/2018)
Regarding claim 12, Nelogal, Dropps and Luo teaches the data management device of claim 11, they do not explicitly teach the limitations of claim 12.
Loh teaches further comprising: a read/write address generator circuit configured to generate the data-address order information (In one example, the region 620 uses the address space 2,000 to 2,700 where the addresses are expressed as digits. The entire last-level cache 130 uses the address space 5,000 to 6,000 where the addresses are also expressed as digits [0065]; For example, in some designs, a first queue stores memory read requests and a second queue stores memory write requests. Logic within the cache controller selects a queue of the one or more queues and selects a memory access request from the selected queue. The logic determines a range of addresses corresponding to a first region of contiguous data stored in system memory [0026]; Each of the logic 336 and the logic 346 is implemented by software, hardware such as circuitry used for combinatorial logic and sequential elements [0048]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Nelogal, Dropps and Luo to incorporate the teachings of Loh for the benefit of improving data transfer rates between these units while reducing power consumption (Loh [0044])
Regarding claim 13, Nelogal, Dropps and Luo teaches the data management device of claim 11, Loh teaches wherein the first memory read request is an artificial neural network data operation request (The accessing of the neural network's weights proceeds in a regular, predictable manner. Therefore, the region in the last-level cache 1130 is increased sufficiently ahead of the evaluation of the weights [0080]; For each memory access of the last-level cache 1330, logic compares the requested address against each valid, supported region in the last-level cache 1330 [0086]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Nelogal, Dropps and Luo to incorporate the teachings of Loh for the benefit of improving data transfer rates between these units while reducing power consumption (Loh [0044])
Regarding claim 14, Nelogal, Dropps and Luo teaches the data management device of claim 11, Luo teaches wherein the data-address order information identifies, in advance, in advance an address of data required for a next artificial neural network data operation (For example, the memory controller 110 may identify, in the subsequently received memory command, a starting address that is also associated with the sequence of memory addresses [0038]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Nelogal, Dropps and Luo to incorporate the teachings of Loh for the benefit of improving data transfer rates between these units while reducing power consumption (Loh [0044])
Regarding claim 15, Nelogal, Dropps and Luo teaches the data management device of claim 11, Loh teaches wherein the processor is one of a central processing unit (CPU), a graphics processing unit (GPU), a neural network processor (NNP), and a customized processor for artificial neural network data operation (Examples of a processing unit are a processor core within a general-purpose central processing unit (CPU), a graphics processing unit (GPU), or other ... One example of such a memory is a 3D integrated memory, such as a 3D DRAM [0040]; In one design example, the weights of a large (deep) neural network are stored in system memory 1110, such as off-package DRAM [0078]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Nelogal, Dropps and Luo to incorporate the teachings of Loh for the benefit of improving data transfer rates between these units while reducing power consumption (Loh [0044])
Regarding claim 16, Nelogal, Dropps and Luo teaches the data management device of claim 11, Dropps teaches wherein the data management device is configured to: determine whether the second memory read request and a third memory read request generated by the processor are a same (The response manager 360 fulfills the future request to the processor nodes 1-N if the subsequent memory action matches the ..., future request for a data block that has been retrieved and stored in a local buffer ... For example, the subsequent memory action can include a memory read [0022]), and
provide the data corresponding to the second memory read request the processor (the request received from the processor node (assuming a match) can be provided to such processor node in a response [0012]).
The same motivation to combine independent claim 11 applies here.
Regarding claim 17, Nelogal, Dropps and Luo teaches the data management device of claim 11, Loh teaches wherein the data stored in the at least one memory includes at least one of a weight, an activation map, and a feature map (Data 1120-1128 are contiguous data stored in the system memory 1110 [0077]; As used herein, “contiguous data” refers to one or more bits of data located next to one another in data storage [0026]; In one design example, the weights of a large (deep) neural network are stored in system memory 1110, such as off-package DRAM [0078]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Neloga, Dropps and Luo to incorporate the teachings of Loh for the benefit of improving data transfer rates between these units while reducing power consumption (Loh [0044])
Regarding claim 18, Nelogal, Dropps and Luo teaches the data management device of claim 11, Loh teaches wherein the data includes data of a multi-layered artificial neural network (In one design example, the weights of a large (deep) neural network are stored in system memory 1110, such as off-package DRAM. The weights, such as data 1120-1128 [0078]) and
an output feature map from a first layer of the multi-layered artificial neural network is temporarily stored in the at least one memory (The last-level cache 1130 stores a copy of a portion of the contiguous data 1120-1128 at different points in time [0077]; The data 1120 corresponds to a first layer of weights of a multi-layer neural network [0078]),
the output feature map is used as an input feature map of a second layer of the multi-layered artificial neural network (The data 1122 corresponds to a second layer of weights of the multi-layer neural network, and so on [0078]; At the later time t1, the data 1122 is added to the region stored in the last-level cache 1130 [0079]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Dropps and Luo to incorporate the teachings of Loh for the benefit of improving data transfer rates between these units while reducing power consumption (Loh [0044])
Regarding claim 19, Nelogal, Dropps and Luo teaches the data management device of claim 1, Loh teaches wherein the first memory read request is an artificial neural network data operation request (The accessing of the neural network's weights proceeds in a regular, predictable manner. Therefore, the region in the last-level cache 1130 is increased sufficiently ahead of the evaluation of the weights [0080]; For each memory access of the last-level cache 1330, logic compares the requested address against each valid, supported region in the last-level cache 1330 [0086]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Dropps and Luo to incorporate the teachings of Loh for the benefit of improving data transfer rates between these units while reducing power consumption (Loh [0044])
6. Claims 8 is rejected under 35 U.S.C. 103 as being unpatentable over Nelogal et al. (US20200285386 filed 03/07/2019) in view of Loh (US20200183848 filed 12/10/2018) in view of Luo et al. (US20200034306 filed 07/24/2018) and further in view of Dropps (US20190114275)
Regarding claim 8, Nelogal, Loh and Luo teaches the data management device of claim 1, Dropps teaches further comprising: a check legitimate access checking sub-circuit configured to check whether address information of the second memory read request and the third memory read request match (The response manager 360 fulfills the future memory request to the processor nodes 1-N if the subsequent memory action matches the future memory request. For example, the subsequent memory action can include a memory read [0022]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Nelogal , Loh and Luo to incorporate the teachings of Dropps in order to save time for the processor nodes in having to access the remote memory themselves and increases the efficiency of access to the remote memory since processor node hand shaking to the node controller when accessing the remote memory can be reduced (Dropps [0012])
7. Claims 6, 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Nelogal et al. (US20200285386 filed 03/07/2019) in view of Loh (US20200183848 filed 12/10/2018) in view of Luo et al. (US20200034306 filed 07/24/2018) and further in view of Shirota et al. (US20180277224 filed 10/17/2017)
Regarding claim 6, Nelogal, Loh and Luo teaches the data management device of claim 1, they do not explicitly teach the limitations of claim 6.
Shirota teaches wherein the data corresponding to the second memory read request is provided to the processor in response to the third memory read request (Upon receiving a read request, the memory controller 40 transfers the data read from the first shared memory 32, the second shared memory 34, or the third shared memory 36 to the processing circuit 22 of the information processing device 20 that has transmitted the access request [0047]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Nelogal, Loh and Luo to incorporate the teachings of Shirota for the benefit of storing data in order to efficiently use the memories having different characteristics in the shared memory (Shirota [0048])
Regarding claim 7, Nelogal, Loh and Luo teaches the data management device of claim 1, they do not explicitly teach the limitations of claim 7.
Shirota teaches wherein the data corresponding to the second memory read request is transmitted to the at least one memory (the processing circuit 22 also transmits the access request according to the first access process to the memory device 30 [0080]) before receiving the third memory read request (the processing circuit 22 of the information processing device 20 transmits the access request according to the second access process [0083]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Nelogal, Loh and Luo to incorporate the teachings of Shirota for the benefit of storing data in order to efficiently use the memories having different characteristics in the shared memory (Shirota [0048])
Regarding claim 9, Nelogal, Loh and Luo teaches the data management device of claim 1, they do not explicitly teach the limitations of claim 9.
Shirota teaches further comprising: a first interface circuit in communication with the processor (a bus as interface circuit between memory controller 40 and processing circuit 22, Fig. 1); and
a second interface circuit in communication with the at least one memory (a bus as interface circuit between memory controller 40 and first shared memory 32, Fig. 1).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Nelogal, Loh and Luo to incorporate the teachings of Shirota for the benefit of storing data in order to efficiently use the memories having different characteristics in the shared memory (Shirota [0048])
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/M.G./Examiner, Art Unit 2148
/MICHELLE T BECHTOLD/ Supervisory Patent Examiner, Art Unit 2148
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