Prosecution Insights
Last updated: October 26, 2026
Application No. 18/231,363

METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE

Non-Final OA §102§103
Filed
Aug 08, 2023
Priority
Aug 16, 2022 — RE 10-2022-0102229
Examiner
BOYLE, ABBIGALE A
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
60%
Grant Probability
Moderate
1-2
OA Rounds
2m
Est. Remaining
72%
With Interview

Examiner Intelligence

Grants 60% of resolved cases
60%
Career Allowance Rate
213 granted / 356 resolved
-8.2% vs TC avg
Moderate +13% lift
Without
With
+12.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
13 currently pending
Career history
401
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
54.6%
+14.6% vs TC avg
§102
25.9%
-14.1% vs TC avg
§112
18.3%
-21.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 356 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 2, 11-17, and 19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 22 June 2026. Information Disclosure Statement The information disclosure statement filed 16 April 2026 fails to comply with 37 CFR 1.98(a)(3)(i) because it does not include a concise explanation of the relevance, as it is presently understood by the individual designated in 37 CFR 1.56(c) most knowledgeable about the content of the information, of each reference listed that is not in the English language. It has been placed in the application file, but the information referred to therein has not been considered. Drawings The drawings are objected to because: The sheets of drawings should be numbered in consecutive Arabic numerals, starting with 1. The drawing sheet numbering must be clear and larger than the numbers used as reference characters to avoid confusion. The number of each sheet should be shown by two Arabic numerals placed on either side of an oblique line, with the first being the sheet number and the second being the total number of sheets of drawings, with no other marking. See Page(s) 1-16. The drawings illustrate a figure comprising two or more independent figures requiring individual designation as separate features and therefore the drawings require a numbering change to the figures. Otherwise, if the multiple figures designated as one represent an exploded view, the figure in question should be properly identified as an exploded view using brackets as objected to supra. For numbering figures, the different views must be numbered in consecutive Arabic numerals, starting with 1, independent of the numbering of the sheets and, if possible, in the order in which they appear on the drawing sheet(s). Refer to 37 CFR 1.84(u). See Figure(s) 2, 12, and 13. The scale of the drawings are too small to adequately show sufficient detail in their current state or when reproduced. The scale to which a drawing is made must be large enough to show the mechanism without crowding when the drawing is reduced in size to two-thirds in reproduction. Refer to 37 CFR 1.84(k). See Figure(s) 15. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: Fan-Out Type Semiconductor Package Having Terminal Solder Bumps Within and Recessed from Encapsulating Layer. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1, and 3-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Han et al. (U.S. 2016/0284657). Regarding Claim 1, Han et al., Figures 2a-e and 3b, discloses a method of manufacturing a semiconductor package, the method comprising: forming a first solder ball on a surface of a redistribution layer (first solder ball 120, RDL 115/116/117/118); forming a preliminary molding layer on the surface of the redistribution layer and the first solder ball (preliminary molding layer 130); exposing the first solder ball and forming a molding layer by grinding the preliminary molding layer and the first solder ball (molding layer 130’, [0078]); and forming a second solder ball by reflowing the first solder ball (second solder ball 120’’’, [0083]), wherein the second solder ball is spaced apart from the molding layer in a horizontal direction (second solder ball 120’’’, molding layer 130’). Regarding Claim 3, Han et al., Figures 2a-e and 3b, further discloses the method of claim 1, wherein the exposing the first solder ball is performed by grinding a portion of a vertical height of the first solder ball ([0080]). Regarding Claim 4, Han et al., Figures 2a-e and 3b, further discloses the method of claim 1, wherein a horizontal length of the second solder ball is less than a horizontal length of the first solder ball (first solder ball 120, second solder ball 120’’’, gap 132). Regarding Claim 5, Han et al., Figures 2a-e and 3b, further discloses the method of claim 1, wherein the molding layer comprises an epoxy molding compound ([0072]). Regarding Claim 6, Han et al., Figures 2a-e and 3b, further discloses the method of claim 1, wherein a thickness of the molding layer is equal to or less than half of a vertical height of the second solder ball (molding layer 130’, second solder ball 120’’’, [0070]). Regarding Claim 7, Han et al., Figures 2a-e and 3b, further discloses the method of claim 1, wherein the molding layer comprises an inner side surface of a ball accommodating space surrounding a portion of the second solder ball, and wherein the inner side surface of the molding layer is concave and faces the redistribution layer (molding compound 130’, inner side surface 131, second solder ball 120’’’, RDL 115/116/117/118, [0086]). Regarding Claim 8, Han et al., Figures 2a-e and 3b, further discloses the method of claim 7, wherein a curvature of the inner side surface of the molding layer is less than a curvature of a surface of the second solder ball (inner side surface 131, second solder ball 120’’’, [0086]). Regarding Claim 9, Han et al., Figures 2a-e and 3b, further discloses the method of claim 1, further comprising forming the redistribution layer by performing a redistribution operation ([0062]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (U.S. 2016/0284657) as applied to claim 1 above, and further in view of Tomono et al. (U.S. 2005/0006789). Regarding Claim 10, Han et al., does not explicitly disclose forming a third solder ball on an exposed surface of the first solder ball, reflowing the first solder ball and the third solder ball, and wherein a diameter of the third solder ball is less than a diameter of the first solder ball and a diameter of the second solder ball. In the same field of endeavor, Tomono et al. discloses forming a third solder ball on an exposed surface of a first solder ball, reflowing the first solder ball and the third solder ball, wherein a diameter of the third solder ball is less than a diameter than the first solder ball and a diameter of the second solder ball (Tomono et al., Figures 9-10, first solder ball 4a, third solder ball 3a, second solder ball 2a/4a, [0033]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a third solder ball on an exposed surface of the first solder ball, reflow the first solder ball and the third solder ball, wherein a diameter of the third solder ball is less than a diameter of the first solder ball and a diameter of the second solder ball in Han et al. in view of Tomono et al. in order to improve device reliability (Tomono et al., [0034]). Claims 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (U.S. 2020/0161275) in view of Han et al. (U.S. 2016/0284657). Regarding Claim 18, Lin et al., Figures 1b, 2c, discloses a method of manufacturing a semiconductor package, the method comprising: forming a first structure comprising a first semiconductor chip and a plurality of second semiconductor chips stacked on the first semiconductor chip (first structure 12, first semiconductor chip 12a, second chips 12b); forming a second structure spaced apart from the first structure in a horizontal direction, the second structure comprising a third semiconductor chip (third semiconductor chip 10); attaching the first structure and the second structure to an interposer (interposer 18); forming a first molding layer and a first solder ball on a lower surface of the interposer (first solder ball 20, first molding layer 56); attaching the interposer to a package base substrate (package base substrate 52); forming a second solder ball on a lower surface of the package base substrate (second solder ball 54), and wherein each of the first molding layer comprises an epoxy molding compound ([0035]). However, they do not explicitly disclose forming a second molding layer on a lower surface of the package base substrate, wherein the second molding layer comprises an epoxy molding compound, wherein the first solder ball is spaced apart from the first molding layer in the horizontal direction, and wherein the second solder ball is spaced apart from the second molding layer in the horizontal direction. In the same field of endeavor, Han et al., discloses a device wherein a molding layer comprising epoxy molding compound and a solder ball are formed on an interposer/package base substrate underneath a structure comprising a semiconductor chip, wherein first solder ball is spaced apart from the molding layer in the horizontal direction (Han et al., Figures 2e and 3b, chip 110, substrate 201, molding compound 130’, solder ball 101, [0072]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the same molding layer/solder ball layer on a lower surface of the interposer and the package base substrate and therefore form a second molding layer on a lower surface of the package base substrate, wherein the second molding layer comprises an epoxy molding compound, wherein the first solder ball is spaced apart from the first molding layer in the horizontal direction, and wherein the second solder ball is spaced apart from the second molding layer in the horizontal direction in Lin et al. in view of Han et al. in order to reduce processing time and cost (Han et al., [0017]) Regarding Claim 20, Lin et al. in view of Han et al. further discloses the method of claim 18, wherein a thickness of the first molding layer is equal to or less than half a vertical height of the first solder ball (Han et al., molding layer 130’, second solder ball 120’’’, [0070]), and wherein a thickness of the second molding layer is equal to or less than half a vertical height of the second solder ball (Han et al., molding layer 130’, second solder ball 120’’’, [0070]). Conclusion Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Abbigale Boyle whose telephone number is 571-270-7919. The Examiner can normally be reached from 11 A.M to 7 P.M., Monday through Friday. If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Zandra Smith, can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance form a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. Abbigale Boyle Examiner, Art Unit 2899 /ABBIGALE A BOYLE/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Aug 08, 2023
Application Filed
Oct 05, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604441
ELECTRONIC CONVERTER DESIGNED ON THE BASIS OF WELDING TECHNOLOGIES
4y 7m to grant Granted Apr 14, 2026
Patent 12550726
PACKAGE CHIP HAVING A HEAT SINK AND METHOD FOR MANUFACTURING PACKAGE CHIP
4y 4m to grant Granted Feb 10, 2026
Patent 12494380
AMPLIFIER MODULES WITH POWER TRANSISTOR DIE AND PERIPHERAL GROUND CONNECTIONS
1y 7m to grant Granted Dec 09, 2025
Patent 12469718
Dense Redistribution Layers in Semiconductor Packages and Methods of Forming the Same
3y 3m to grant Granted Nov 11, 2025
Patent 12438008
METHOD OF PRODUCING ASSEMBLY OF STACKED ELEMENTS HAVING RESIN LAYER WITH FILLERS
1y 3m to grant Granted Oct 07, 2025
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
60%
Grant Probability
72%
With Interview (+12.6%)
3y 5m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 356 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month