DETAILED ACTION
This action is responsive to U.S. Patent Application No. 18/231,472 filed on 8 August 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of Applicant's Information Disclosure Statement(s) (IDS). The IDS(es) has/have been considered.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Applicant’s election without traverse of the Species 1 embodiment in the reply filed on 23 December 2025 is acknowledged.
Accordingly, claims 7 and 14, directed to a nonelected embodiment, are withdrawn from further consideration.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the claimed features:
Of claim 1: “a light emitting element in the emission area, the light emitting element configured to emit light”;
Of claim 3: “the light blocking layer between the substrate and the active layer of the driving transistor”;
Of claim 5: “wherein the second capacitor electrode is on a same layer as the active layer of the driving transistor”;
Of claim 9: “wherein an area of the first capacitor electrode is greater than an area of the second capacitor electrode”;
Of claim 10: “a third capacitor electrode extending from the first capacitor electrode”;
Of claim 10: “a fourth capacitor electrode extending from the second capacitor electrode”;
Of claim 11: “wherein the third capacitor electrode is integrally formed with the light blocking layer”;
Of claim 12: “wherein the third capacitor electrode comprises a transparent oxide layer and a metal layer that is stacked on the transparent oxide layer”;
Of claim 15: “a fifth capacitor electrode that overlaps the fourth capacitor electrode and is on a same layer as a gate electrode of the driving transistor”;
Of claim 16: “a light emitting element on the substrate in the emission area, the light emitting element configured to emit light”;
Of claim 16: “a first electrode on the substrate, the first electrode having a first portion in the emission area and a second portion in the non-emission area; a second electrode on the substrate, the second electrode having a first portion in the emission area and a second portion in the non-emission area”;
Of claim 18: “the buffer layer extending across the emission area and the non-emission area”;
Of claim 18: “the semiconductor layer extending across the emission area and non-emission area”;
Of claim 20: “a light emitting element on the substrate in the emission area, the light emitting element configured to emit light”;
Of claim 20: “the first storage capacitor connected between the driving transistor and the light emitting element”;
Of claim 20: “the second storage capacitor connected between the driving transistor and the light emitting element”;
Of claim 21: “wherein the first electrode and the third electrode are electrically connected, and the second electrode and the fourth electrode are electrically connected”;
Of claim 23: “the buffer layer extending across the emission area and non-emission area”;
Of claim 23: “the semiconductor layer extending across the emission area and the non-emission area”;
must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 9-11, and 15-24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Publication No. 2018/0061908 (published Mar. 1, 2018) (hereinafter “Shim”).
Regarding independent claim 1, Shim discloses: A display device, comprising:
a substrate (FIGS. 11/12, substrate SUB, [0078]) including an emission area (FIG. 12, depicting a first area, e.g., that portion of the substrate under the overcoat layer OC) and a non-emission area (FIG. 12, depicting a second area, e.g., that portion of the substrate not under the overcoat layer OC), the emission area comprising a sub-pixel (FIG. 12, depicting wherein the first area includes a sub-pixel SPn1, [0057]);
a light emitting element (FIG. 12, organic light emitting diode OLED, [0003]) in the emission area (FIG. 12, depicting wherein the OLED is in the first area), the light emitting element configured to emit light (FIG. 12, [0003]: “In more detail, an OLED display is a self-emission display device emitting light by exciting an organic compound.”);
a driving transistor (FIGS. 11/12, driving transistor DR, [0044]) in the non-emission area (FIGS. 11/12, depicting wherein the driving transistor DR is in the second area), the driving transistor configured to drive the light emitting element (FIGS. 11/12, [0044]: “The organic light emitting diode OLED emits light depending on the driving current formed by the driving transistor DR.”);
a first storage capacitor (FIGS. 11/12, depicting, e.g., that portion of the first capacitor C1 in the first area, [0075]) in the emission area (FIGS. 11/12, depicting wherein at least a portion of the first capacitor C1 is disposed in the first area); and
a second storage capacitor (FIGS. 11/12, depicting, e.g., that portion of the first capacitor C1 in the second area, [0075]) in the non-emission area (FIGS. 11/12, depicting wherein at least a portion of the first capacitor C1 is disposed in the second area).
Regarding claim 2, Shim further discloses a buffer layer (FIGS. 11/12, buffer layer BUF, [0069]) on the substrate (FIGS. 11/12, depicting wherein the buffer layer BUF is on the substrate SUB), wherein the first storage capacitor (FIGS. 11/12, depicting, e.g., that portion of the first capacitor C1 in the first area, [0075]) includes a first capacitor electrode (FIGS. 11/12, light shielding layer LS, [0054]) between the substrate and the buffer layer (FIGS. 11/12, depicting wherein the light shielding layer LS is between the substrate SUB and the buffer layer BUF).
Regarding claim 3, Shim further discloses wherein the driving transistor comprises an active layer (FIGS. 11/12, depicting a portion of the semiconductor layer ACT3 overlapping a gate electrode GAT2, [0066]), the display device further comprising: a light blocking layer (FIGS. 11/12, light shielding layer LS) in the non-emission area (FIGS. 11/12, depicting wherein the light shielding layer LS is in the second area), the light blocking layer between the substrate and the active layer of the driving transistor (FIGS. 11/12, depicting wherein the light shielding layer LS is between the substrate SUB and the buffer layer BUF), wherein the first storage capacitor is on a same layer as the light blocking layer (FIGS. 11/12, depicting wherein the first capacitor C1 is on a same layer as the light shielding layer LS).
Regarding claim 4, Shim further discloses wherein the first storage capacitor (FIGS. 11/12, first capacitor C1) further includes a second capacitor electrode (FIGS. 11/12, semiconductor layer ACT3) on the buffer layer (FIGS. 11/12, depicting wherein the semiconductor layer ACT3 is disposed on the buffer layer BUF), the second capacitor electrode overlapping the first capacitor electrode (FIGS. 11/12, depicting wherein the semiconductor layer ACT3 overlaps the light shielding layer LS).
Regarding claim 5, Shim further discloses wherein the second capacitor electrode (FIGS. 11/12, semiconductor layer ACT3) is on a same layer as the active layer of the driving transistor (FIGS. 11/12, depicting wherein the portion of the semiconductor layer ACT3 not overlapping the gate electrode GAT2 is on a same layer as the portion of the semiconductor layer ACT3 overlapping the gate electrode GAT2).
Regarding claim 9, Shim further discloses wherein an area of the first capacitor electrode is greater than an area of the second capacitor electrode (FIGS. 11/12, depicting wherein an area of the light shielding layer LS is greater than an area of the semiconductor layer ACT3).
Regarding claim 10, Shim further discloses wherein the second storage capacitor (FIGS. 11/12, depicting, e.g., that portion of the first capacitor C1 in the second area, [0075]) includes: a third capacitor electrode (FIGS. 11/12, light shielding layer LS) extending from the first capacitor electrode and on a same layer as the first capacitor electrode (FIGS. 11/12, depicting wherein the portion of the light shielding layer LS forming the portion of the first capacitor C1 in the second area extends in a direction away from that portion of the light shielding layer LS forming the portion of the first capacitor C1 in the first area and is on the same layer as the light shielding layer LS forming the portion of the first capacitor C1 in the first area); and a fourth capacitor electrode (FIGS. 11/12, semiconductor layer ACT3) extending from the second capacitor electrode and on a same layer as the second capacitor electrode (FIGS. 11/12, depicting wherein the semiconductor layer ACT3 forming the portion of the first capacitor C1 in the second area extends in a direction away from that portion of the semiconductor layer ACT3 forming the portion of the first capacitor in the second area and is on a same layer as the semiconductor layer ACT3 forming the portion of the first capacitor C1 in the first area).
Regarding claim 11, Shim further discloses wherein the third capacitor electrode is integrally formed with the light blocking layer (FIGS. 11/12, depicting wherein the light shielding layer is also a capacitor electrode, [0054]).
Regarding claim 15, Shim further discloses wherein the second storage capacitor further includes a fifth capacitor electrode (FIGS. 11/12, electrode SWDE, [0065]) that overlaps the fourth capacitor electrode (FIGS. 11/12, depicting wherein the electrode SWDE overlaps the semiconductor layer ACT3) and is on a same layer as a gate electrode of the driving transistor (FIGS. 11/12, depicting wherein the electrode SWDE is on a same layer, e.g., dielectric layer ILD, as the gate electrode GAT2).
Regarding independent claim 16, Shim discloses: A display device, comprising:
a substrate (FIGS. 11/12, substrate SUB, [0078]) having an emission area (FIG. 12, depicting a first area, e.g., that portion of the substrate under the overcoat layer OC) and a non-emission area (FIG. 12, depicting a second area, e.g., that portion of the substrate not under the overcoat layer OC);
a light emitting element (FIG. 12, organic light emitting diode OLED, [0003]) in the emission area (FIG. 12, depicting wherein the OLED is in the first area), the light emitting element configured to emit light (FIG. 12, [0003]: “In more detail, an OLED display is a self-emission display device emitting light by exciting an organic compound.”);
a driving transistor (FIGS. 11/12, driving transistor DR, [0044]) on the substrate in the non-emission area (FIGS. 11/12, depicting wherein the driving transistor DR is in the second area), the driving transistor configured to drive the light emitting element (FIGS. 11/12, [0044]: “The organic light emitting diode OLED emits light depending on the driving current formed by the driving transistor DR.”);
a first electrode on the substrate (FIGS. 11/12, semiconductor layer ACT3 on the substrate SUB, [0066]), the first electrode having a first portion in the emission area and a second portion in the non-emission area (FIGS. 11/12, depicting wherein the semiconductor layer ACT3 has a first portion in the first area and a second portion in the second area);
a second electrode on the substrate (FIGS. 11/12, light shielding layer LS on the substrate SUB, [0054]), the second electrode having a first portion in the emission area and a second portion in the non-emission area (FIGS. 11/12, depicting wherein the light shielding layer LS has a first portion in the first area and a second portion in the second area),
wherein the first portion of the first electrode and the first portion of the second electrode overlap each other in the emission area such that a first storage capacitor is in the emission area (FIGS. 11/12, depicting wherein the first portions of the light shielding layer LS and semiconductor layer ACT3 overlap to form that portion of the first capacitor C1 in the first area, [0075]), and
the second portion of the first electrode and the second portion of the second electrode overlap each other in the non-emission area such that a second storage capacitor is in the non-emission area (FIGS. 11/12, depicting wherein the second portions of the light shielding layer LS and semiconductor layer ACT3 overlap to form that portion of the first capacitor C1 in the second area, [0075]).
Regarding claim 17, Shim further discloses wherein the first portion and the second portion of the second electrode are directly on the substrate (FIGS. 11/12, depicting wherein the light shielding layer LS is directly on the substrate SUB).
Regarding claim 18, Shim further discloses a buffer layer on the second electrode (FIGS. 11/12, buffer layer BUF on the light shielding layer LS), the buffer layer extending across the emission area and the non-emission area (FIGS. 11/12, depicting wherein the buffer layer BUF extends across the first and second areas); a semiconductor layer on the buffer layer (FIGS. 11/12, depicting, e.g., electrode ANO formed of, e.g., IZO, [0077]), the semiconductor layer extending across the emission area and non-emission area (FIGS. 11/12, depicting wherein the electrode ANO extends across the first and second areas); and a light blocking layer between the buffer layer and the second electrode in the non-emission area (FIGS. 11/12, depicting, e.g., that portion of the electrode SWDE in the contact hole SWCH3 which is between the buffer layer BUF and the light shielding layer LS in the second area, formed from light blocking material such as Al, Cr, AU, Ti, Ni, Nd, Cu, etc., [0071]), wherein the first portion and the second portion of the first electrode are on the semiconductor layer (FIGS. 11/12, depicting wherein the first and second portions of the semiconductor layer ACT3 are on the electrode ANO).
Regarding claim 19, Shim further discloses a gate insulating layer on the first electrode (FIGS. 11/12, interlayer dielectric layer ILD on the semiconductor layer ACT3, [0072]); and a third electrode on the gate insulating layer in the non-emission area (FIGS. 11/12, e.g., electrode SWDE on the interlayer dielectric layer ILD in the second area), the third electrode overlapping the second portion of the first electrode (FIGS. 11/12, depicting wherein the electrode SWDE overlaps the second portion of the semiconductor layer ACT3).
Regarding independent claim 20, Shim discloses: A display device, comprising:
a substrate (FIGS. 11/12, substrate SUB, [0078]) having an emission area (FIG. 12, depicting a first area, e.g., that portion of the substrate under the overcoat layer OC) and a non-emission area (FIG. 12, depicting a second area, e.g., that portion of the substrate not under the overcoat layer OC);
a light emitting element (FIG. 12, organic light emitting diode OLED, [0003]) on the substrate in the emission area (FIG. 12, depicting wherein the OLED is in the first area), the light emitting element configured to emit light (FIG. 12, [0003]: “In more detail, an OLED display is a self-emission display device emitting light by exciting an organic compound.”);
a driving transistor (FIGS. 11/12, driving transistor DR, [0044]) on the substrate in the non-emission area (FIGS. 11/12, depicting wherein the driving transistor DR is in the second area), the driving transistor configured to drive the light emitting element (FIGS. 11/12, [0044]: “The organic light emitting diode OLED emits light depending on the driving current formed by the driving transistor DR.”);
a first storage capacitor (FIGS. 11/12, depicting, e.g., that portion of the first capacitor C1 in the first area, [0075]) in the emission area (FIGS. 11/12, depicting wherein at least a portion of the first capacitor C1 is disposed in the first area), the first storage capacitor connected between the driving transistor and the light emitting element (FIGS. 11/12, depicting wherein that portion of the first capacitor C1 in the first area is connected between the driving transistor DR and the OLED); and
a second storage capacitor (FIGS. 11/12, depicting, e.g., that portion of the first capacitor C1 in the second area, [0075]) in the non-emission area (FIGS. 11/12, depicting wherein at least a portion of the first capacitor C1 is disposed in the second area), the second storage capacitor connected between the driving transistor and the light emitting element (FIGS. 11/12, depicting wherein that portion of the first capacitor C1 in the second area is connected between the driving transistor DR and the OLED).
Regarding claim 21, Shim further discloses wherein the first storage capacitor includes a first electrode (FIGS. 11/12, that portion of the light shielding layer LS in the first area, [0054]) and a second electrode (FIGS. 11/12, that portion of the semiconductor layer ACT3 in the first area), and the second storage capacitor comprising a third electrode (FIGS. 11/12, that portion of the light shielding layer LS in the second area) and a fourth electrode (FIGS. 11/12, that portion of the semiconductor layer ACT3 in the first area), wherein the first electrode and the third electrode are electrically connected (FIGS. 11/12, depicting wherein the portions of the light shielding layer LS in the first and second areas are electrically connected), and the second electrode and the fourth electrode are electrically connected (FIGS. 11/12, depicting wherein the potions of the semiconductor layer ACT3 in the first and second areas are electrically connected).
Regarding claim 22, Shim further discloses wherein the first electrode and the third electrode are directly on the substrate (FIGS. 11/12, depicting wherein the portions of the light shielding layer LS in the first and second areas are directly on the substrate SUB).
Regarding claim 23, Shim further discloses a buffer layer on the first electrode (FIGS. 11/12, buffer layer BUF on the light shielding layer LS), the buffer layer extending across the emission area and non-emission area (FIGS. 11/12, depicting wherein the buffer layer BUF extends across the first and second areas); a semiconductor layer on the buffer layer (FIGS. 11/12, depicting, e.g., electrode ANO formed of, e.g., IZO, [0077]), the semiconductor layer extending across the emission area and the non-emission area (FIGS. 11/12, depicting wherein the electrode ANO extends across the first and second areas); and a light blocking layer between the buffer layer and the first electrode in the non-emission area (FIGS. 11/12, depicting, e.g., that portion of the electrode SWDE in the contact hole SWCH3 which is between the buffer layer BUF and the light shielding layer LS in the second area, formed from light blocking material such as Al, Cr, AU, Ti, Ni, Nd, Cu, etc., [0071]), wherein the second electrode and the fourth electrode are on the semiconductor layer (FIGS. 11/12, depicting wherein the first and second portions of the semiconductor layer ACT3 are on the electrode ANO).
Regarding claim 24, Shim further discloses a gate insulating layer on the second electrode (FIGS. 11/12, interlayer dielectric layer ILD on the semiconductor layer ACT3, [0072]); wherein the second storage capacitor further comprises a fifth electrode on the gate insulating layer in the non-emission area (FIGS. 11/12, e.g., electrode SWDE on the interlayer dielectric layer ILD in the second area), the fifth electrode overlapping the fourth electrode (FIGS. 11/12, depicting wherein the electrode SWDE overlaps the second portion of the semiconductor layer ACT3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, 8, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Shim in view of U.S. Patent Publication No. 2022/0416195 (filed May 5, 2021) (hereinafter “Zhang”).
Regarding claim 6, Shim does not specifically disclose wherein the second capacitor electrode comprises a transparent oxide layer.
In the same field of endeavor, Zhang discloses a display device including an electrode (FIG. 2, electrode 2, [0068]) comprising a plurality of stacked conductive layers, wherein one conductive layer comprises a light blocking metal material (FIG. 2, top conductive layer 21, [0068]) and another conductive layer comprises a transparent conductive oxide material (FIG. 2, top conductive layer 22, [0068]). Regarding the configuration of the electrode, in [0068], Zhang states: “Therefore, in order to avoid oxidation corrosion of the patterned first electrodes, in the display panel provided by the embodiment of the present disclosure, as shown in FIG. 2 , each first electrode 2 includes two conductive layers arranged in a stacked manner. A material of the top conductive layer 22 may include one or a combination of ITO, IZO, IGZO, TiN or Mo, and a material of the bottom conductive layer 21 may include one or a combination of Al, AlNd, Mo, Ti or TiN.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor layer ACT3 of Shim by substituting the electrode configuration of Zhang in order to improve corrosion resistance of the light shielding layer. See Zhang [0068].
Regarding claim 8, Shim does not specifically disclose wherein the first capacitor electrode comprises a transparent conductive material.
In the same field of endeavor, Zhang discloses a display device including an electrode (FIG. 2, electrode 2, [0068]) comprising a plurality of stacked conductive layers, wherein one conductive layer comprises a light blocking metal material (FIG. 2, top conductive layer 21, [0068]) and another conductive layer comprises a transparent conductive oxide material (FIG. 2, top conductive layer 22, [0068]). Regarding the configuration of the electrode, in [0068], Zhang states: “Therefore, in order to avoid oxidation corrosion of the patterned first electrodes, in the display panel provided by the embodiment of the present disclosure, as shown in FIG. 2 , each first electrode 2 includes two conductive layers arranged in a stacked manner. A material of the top conductive layer 22 may include one or a combination of ITO, IZO, IGZO, TiN or Mo, and a material of the bottom conductive layer 21 may include one or a combination of Al, AlNd, Mo, Ti or TiN.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the light shielding layer LS of Shim by substituting the electrode configuration of Zhang in order to improve corrosion resistance of the light shielding layer. See Zhang [0068].
Further, Shim does not specifically disclose wherein the second capacitor electrode comprises a transparent conductive material.
In the same field of endeavor, Zhang discloses a display device including an electrode (FIG. 2, electrode 2, [0068]) comprising a plurality of stacked conductive layers, wherein one conductive layer comprises a light blocking metal material (FIG. 2, top conductive layer 21, [0068]) and another conductive layer comprises a transparent conductive oxide material (FIG. 2, top conductive layer 22, [0068]). Regarding the configuration of the electrode, in [0068], Zhang states: “Therefore, in order to avoid oxidation corrosion of the patterned first electrodes, in the display panel provided by the embodiment of the present disclosure, as shown in FIG. 2 , each first electrode 2 includes two conductive layers arranged in a stacked manner. A material of the top conductive layer 22 may include one or a combination of ITO, IZO, IGZO, TiN or Mo, and a material of the bottom conductive layer 21 may include one or a combination of Al, AlNd, Mo, Ti or TiN.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor layer ACT3 of Shim by substituting the electrode configuration of Zhang in order to improve corrosion resistance of the light shielding layer. See Zhang [0068].
Regarding claim 12, Shim does not specifically disclose wherein the third capacitor electrode comprises a transparent oxide layer and a metal layer that is stacked on the transparent oxide layer.
In the same field of endeavor, Zhang discloses a display device including an electrode (FIG. 2, electrode 2, [0068]) comprising a plurality of stacked conductive layers, wherein one conductive layer comprises a light blocking metal material (FIG. 2, top conductive layer 21, [0068]) and another conductive layer comprises a transparent conductive oxide material (FIG. 2, top conductive layer 22, [0068]). Regarding the configuration of the electrode, in [0068], Zhang states: “Therefore, in order to avoid oxidation corrosion of the patterned first electrodes, in the display panel provided by the embodiment of the present disclosure, as shown in FIG. 2 , each first electrode 2 includes two conductive layers arranged in a stacked manner. A material of the top conductive layer 22 may include one or a combination of ITO, IZO, IGZO, TiN or Mo, and a material of the bottom conductive layer 21 may include one or a combination of Al, AlNd, Mo, Ti or TiN.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the light shielding layer LS of Shim by substituting the electrode configuration of Zhang in order to improve corrosion resistance of the light shielding layer. See Zhang [0068].
Regarding claim 13, Shim does not specifically disclose wherein the fourth capacitor electrode comprises a transparent oxide layer.
In the same field of endeavor, Zhang discloses a display device including an electrode (FIG. 2, electrode 2, [0068]) comprising a plurality of stacked conductive layers, wherein one conductive layer comprises a light blocking metal material (FIG. 2, top conductive layer 21, [0068]) and another conductive layer comprises a transparent conductive oxide material (FIG. 2, top conductive layer 22, [0068]). Regarding the configuration of the electrode, in [0068], Zhang states: “Therefore, in order to avoid oxidation corrosion of the patterned first electrodes, in the display panel provided by the embodiment of the present disclosure, as shown in FIG. 2 , each first electrode 2 includes two conductive layers arranged in a stacked manner. A material of the top conductive layer 22 may include one or a combination of ITO, IZO, IGZO, TiN or Mo, and a material of the bottom conductive layer 21 may include one or a combination of Al, AlNd, Mo, Ti or TiN.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the light shielding layer LS of Shim by substituting the electrode configuration of Zhang in order to improve corrosion resistance of the light shielding layer. See Zhang [0068].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Publication Nos.: 2018/0033849; 2022/0208922; 2023/0122411; 2022/0181420; 2016/0372497.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM D WEILAND whose telephone number is (703)756-4760. The examiner can normally be reached Monday - Friday 9am-5pm.
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/ADAM D WEILAND/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813