DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 2/6/2026 have been fully considered but they are not persuasive. Applicant’s first argument is as follows:
“…para. [0026] of Applicant's published specification describes that "The periphery of each FET inside a stack is independently trimmed to provide more states with less complexity in terms of eased control and number of components ... In other words, an area efficient way of trimming for gain or attenuation is provided (emphasis added)."
In rejecting the previously presented independent claim 1, the Office Action asserts that different embodiments of Cam's stack of MOS transistors in Figure 3. having different numbers of multiple stacked transistors, teach "a first field-effect transistor (FET)" and "a second FET." (Office Action. Page 4). However, Cam's stack of MOS transistors is not "a single FET" and does not have an "independently trimmed periphery." Rather. Cam's stack of MOS transistors includes "a plurality of transistors 210" (para. [0017]) and is therefore not "a single FET."
In Applicant’s 5/8/2025 Remarks, in response to the rejection under §112, trimming the periphery was described as referring to changing the number of fingers of individual FETs (pg. 8), wherein:
“…to change the number of fingers of an FET-based variable switch as taught by Applicant's published specification, an ordinary artisan would understand it to mean, in one example, replacing an FET of the variable switch having a number of fingers with another FET having a different number of fingers and, in another example, combining multiple FETs through various connection topologies (in series, in parallel, etc.)” pg. 9.
In both examples provided by the Applicant, a FET having an independently trimmed periphery requires at least two FETs.
Since no other examples have been provided by Applicant’s disclosure or in the prosecution history, the limitation of “a field-effect transistor (FET) having a first independently trimmed periphery and a second FET…each of the fist and second FETs being a single FET” as claimed is not enabled, as will be further discussed in the §112 rejection below.
Applicant’s second argument is as follows:
“Moreover, Cam does not even mention periphery trimming at all. Thus, even if one of the transistors 210 inside Cam's stack of MOS transistors may perhaps be interpreted as "a single FET," there is still no teaching in Cam of different individual transistors 210 each having a different "independently trimmed periphery." Therefore, Cam does not teach or suggest "a first field-effect transistor (FET) having a first independently trimmed periphery and a second FET having a second independently trimmed periphery different than the first independently trimmed periphery," as is recited in currently amended independent claim 1. Neither Srirattana nor Lopata cures the deficiencies of Cam. For at least these reasons, currently amended independent claim 1 is allowable.”
¶11-17 of the 11/13/2025 Non-Final Rejection teaches that Srirattana fails to teach the first and second FET having different numbers of fingers. Lopata and Cam teach that a stack of MOS transistors can be used to implement a resistor wherein the resistance value is adjust based on the number of individual transistors within the stack. The combination of Srirattana, Lopata and Cam teaches a different number of transistors being used to implement the claimed first and second FETs.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claims 1, 13 and 18 (and by virtue of dependence, all the claims) require “a field-effect transistor (FET) having a first independently trimmed periphery and a second FET having a second independently trimmed periphery different than the first independently trimmed periphery, each of the first and second FETs being a single FET”. However, Applicant has not explained how a single transistor can have independently trimmed periphery.
For the purposes of examination, examiner will omit the limitation “each of the first and second FETs being a single FET” from the claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Srirattana (US 2017/0250723) in view of Cam et al (US 2016/0085256) and Lopata (US 2003/0184363)
For claim 1, Srirattana teaches a switched attenuator (Figure 6) comprising:
a radio frequency (RF) input (left terminal of left R3);
an RF output (right terminal of right R3); and
an attenuation cell (400) connected between the RF input and the RF output and including a variable switch (R2b, R2c, R2cal) with a variable on-resistance (based on enabling or disabling the switches within R2b, R2c and R2cal), the variable switch including a first element (R2C, [0055]) and a second element (R2cal, [0055]), the variable switch being configured to enable the first element and disable the second element in a first mode of operation (when R2b and R2C are enabled and R2cal is disabled, [0061]) and enable the second element and disable the first element in a second mode of operation to fine-tune the variable on-resistance of the variable switch (when R2b and R2cal is enabled and R2c is disabled, [0061]).
Srirattana fails to teach:
the variable switch being configured to enable a first field-effect transistor (FET) having a first independently trimmed periphery and a second FET having a second independently trimmed periphery different than the first.
Lopata teaches that resistors can be “implemented using active devices (e.g., transistors) that are biased at a predetermined quiescent operating point, preferably in a linear region of operation” ([0025]).
Cam teaches a stack of MOS transistors (Figure 3) wherein the total resistance of the stack is based the sum of the individual transistors ([0008]) and a common bias voltage is applied to the gates of said MOS transistors ([0017]).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to implement each of the resistors within Srirattana’s R2c and R2cal using Cam’s stack of MOS transistors having a common bias voltage applied thereto since the substitution of one known element for another would have yielded predictable results to one of ordinary skill in the art at the time of the invention, as evidenced by Lopata.
It is noted that since the resistors corresponding to R2c and R2cal are substantially different in value (e.g., R2c is 30.04Ω and R2cal is 200Ω, [0061] and Table 2), a different number of stacked transistors would be need to provide the required resistance values. Thus, the MOS stack used within R2c would have a different number of fingers than that of the MOS stack used within R2cal.
Note that Applicant’s 5/8/2025 arguments states that “to change the number of fingers …an ordinary artisan would understand it to mean…combining multiple FETs through various connection topologies (in series, in parallel, etc.)” (pg. 9).
For claim 2, the combination of Srirattana and Cam in view of Lopata teaches the limitations of claim 1 and further teaches:
the variable switch is configured for fine trimming an insertion loss of the variable switch (due to, e.g., manufacturing variations, [0061] of Srirattana).
For claim 3, the combination of Srirattana and Cam in view of Lopata teaches the limitations of claim 1 and Srirattana further teaches:
the attenuation cell comprises an attenuation network, the attenuation network optionally comprising at least one of a PI- network, a T- network, and a bridged T-network (R1 and R3 form a T-network).
For claim 4, the combination of Srirattana and Cam in view of Lopata teaches the limitations of claim 3 and Srirattana further teaches:
the attenuation network comprises two impedances connected in series between input and output terminals of the attenuation network (both instances of R3).
For claim 5, the combination of Srirattana and Cam in view of Lopata teaches the limitations of claim 4 and Srirattana further teaches:
the attenuation network further comprises a bridge impedance connected between the input and the output terminals of the attenuation network (R2a).
For claim 6, the combination of Srirattana and Cam in view of Lopata teaches the limitations of claim 5 and Srirattana further teaches:
the two series connected impedances and the bridge impedance are connected in parallel between the input and the output terminals of the attenuation network (as understood by examination of Figure 6).
For claim 7, the combination of Srirattana and Cam in view of Lopata teaches the limitations of claim 3 and Srirattana further teaches:
the variable switch is connected between input and output terminals of the attenuation network (as understood by examination of Figure 6).
For claim 8, the combination of Srirattana and Cam in view of Lopata teaches the limitations of claim 4 and Srirattana further teaches:
the attenuation network comprises a shunt impedance coupled between the two series connected impedances (R1).
For claim 9, the combination of Srirattana and Cam in view of Lopata teaches the limitations of claim 1 and further teaches:
the variable switch comprises a stack of a plurality of FETs, the plurality of FETs including at least one of the first FET and the second FET (see rejection of claim 1).
For claim 10, the combination of Srirattana and Cam in view of Lopata teaches the limitations of claim 9 and further teaches:
the at least one of the first FET and the second FET comprises a trimmed on-resistance forming, at least in part, the variable on-resistance of the variable switch (bias voltage received at the gates of the stacked transistors, see rejection of claim 1).
For claim 11, the combination of Srirattana and Cam in view of Lopata teaches the limitations of claim 10 and further teaches:
one of the plurality of FETs has a fixed on-resistance forming (via a bias voltage applied to the gate terminal), at least in part, the variable on-resistance of the variable switch (see rejection of claim 1).
For claim 12, the combination of Srirattana and Cam in view of Lopata teaches the limitations of claim 9 and further teaches:
the variable on- resistance of the variable switch is equal to a sum of a respective on-resistance of each of the plurality of FETs of the stack (see rejection of claim 1).
For claim 13, Srirattana teaches a method of controlling a switched attenuator (Figure 6) comprising a radio frequency (RF) input (left terminal of left R3), a RF output (right terminal of right R3), and an attenuation cell (400) connected between the RF input and the RF output and including a variable switch (R2b, R2c, R2cal) with a variable on-resistance (based on enabling or disabling the switches within R2c and R2cal), the method comprising:
fine-tuning the variable on-resistance of the variable switch (via enabling or disabling R2b, R2c and R2cal), the fine-tuning including
enabling a first element of the variable switch (R2C, [0055]) and disabling a second element of the variable switch (within R2cal, [0055]) in a first mode of operation (when R2b and R2C are enabled and R2cal is disabled, [0061]), and disabling the first FET and enabling the second FET in a second mode of operation (when R2b and R2cal is enabled and R2b is disabled, [0061]).
Srirattana fails to teach:
enabling a first FET of the variable switch having a first independently trimmed periphery and disabling a second FET of the variable switch having a second independently trimmed periphery different than the first independently trimmed periphery in a first mode of operation.
Lopata teaches that resistors can be “implemented using active devices (e.g., transistors) that are biased at a predetermined quiescent operating point, preferably in a linear region of operation” ([0025]).
Cam teaches a stack of MOS transistors (Figure 3) wherein the total resistance of the stack is based the sum of the individual transistors ([0008]) and a common bias voltage is applied to the gates of said MOS transistors ([0017]).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to implement each of the resistors within Srirattana’s R2c and R2cal using Cam’s stack of MOS transistors having a common bias voltage applied thereto since the substitution of one known element for another would have yielded predictable results to one of ordinary skill in the art at the time of the invention, as evidenced by Lopata.
It is noted that since the resistors corresponding to R2c and R2cal are substantially different in value (e.g., R2c is 30.04Ω and R2cal is 200Ω, [0061] and Table 2), a different number of stacked transistors would be need to provide the required resistance values. Thus, the MOS stack used within R2c would have a different number of fingers than that of the MOS stack used within R2cal.
Note that Applicant’s 5/8/2025 arguments states that “to change the number of fingers …an ordinary artisan would understand it to mean…combining multiple FETs through various connection topologies (in series, in parallel, etc.)” (pg. 9).
For claim 14, the combination of Srirattana and Cam in view of Lopata teaches the limitations of claim 13 and further teaches:
the variable switch comprises a stack of a plurality of FETs, the plurality of FETs including at least one of the first FET and the second FET (see rejection of claim 13).
For claim 15, the combination of Srirattana and Cam in view of Lopata teaches the limitations of claim 14 and further teaches:
the at least one of the first FET and the second FET comprises a trimmed on-resistance forming, at least in part, the variable on-resistance of the variable switch (bias voltage received at the gates of the stacked transistors, see rejection of claim 13).
For claim 16, the combination of Srirattana and Cam in view of Lopata teaches the limitations of claim 15 and further teaches:
one of the plurality of FETs has a fixed on-resistance forming (via a bias voltage applied to the gate terminal), at least in part, the variable on-resistance of the variable switch (see rejection of claim 13).
For claim 17, the combination of Srirattana and Cam in view of Lopata teaches the limitations of claim 14 and further teaches:
the variable on- resistance of the variable switch is equal to a sum of a respective on-resistance of each of the plurality of FETs of the stack (see rejection of claim 13).
For claim 18, Srirattana teaches a mobile device ([0077]) including a switched attenuator (Figure 6) comprising:
a radio frequency (RF) input (left terminal of left R3);
a RF output (right terminal of right R3);
and an attenuation cell (400) connected between the RF input and the RF output and including a variable switch (R2b, R2c, R2cal) with a variable on-resistance (based on enabling or disabling the switches within R2c and R2cal), the variable switch including a first element (R2C, [0055]) and a second element (R2cal, [0055]), the variable switch being configured to fine-tune the variable on resistance of the variable switch (via enabling or disabling R2c and R2cal), the fine-tuning including:
enabling the first FET and disabling a second FET in a first mode of operation (when R2b and R2C are enabled and R2cal is disabled, [0061]), and disabling the first FET and enabling the second FET in a second mode of operation (when R2b and R2cal is enabled and R2b is disabled, [0061]).
Srirattana fails to teach:
the variable switch including a first field-effect transistor (FET) having a first independently trimmed periphery and a second FET having a second independently trimmed periphery.
Lopata teaches that resistors can be “implemented using active devices (e.g., transistors) that are biased at a predetermined quiescent operating point, preferably in a linear region of operation” ([0025]).
Cam teaches a stack of MOS transistors (Figure 3) wherein the total resistance of the stack is based the sum of the individual transistors ([0008]) and a common bias voltage is applied to the gates of said MOS transistors ([0017]).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to implement each of the resistors within Srirattana’s R2c and R2cal using Cam’s stack of MOS transistors having a common bias voltage applied thereto since the substitution of one known element for another would have yielded predictable results to one of ordinary skill in the art at the time of the invention, as evidenced by Lopata.
It is noted that since the resistors corresponding to R2c and R2cal are substantially different in value (e.g., R2c is 30.04Ω and R2cal is 200Ω, [0061] and Table 2), a different number of stacked transistors would be need to provide the required resistance values. Thus, the MOS stack used within R2c would have a different number of fingers than that of the MOS stack used within R2cal.
Note that Applicant’s 5/8/2025 arguments states that “to change the number of fingers …an ordinary artisan would understand it to mean…combining multiple FETs through various connection topologies (in series, in parallel, etc.)” (pg. 9).
For claim 19, the combination of Srirattana and Cam in view of Lopata teaches the limitations of claim 18 and further teaches:
the variable switch comprises a stack of a plurality of FETs, the plurality of FETs including at least one of the first FET and the second FET (see rejection of claim 18).
For claim 20, the combination of Srirattana and Cam in view of Lopata teaches the limitations of claim 19 and further teaches:
the variable on- resistance of the variable switch is equal to a sum of a respective on-resistance of each of the plurality of FETs of the stack (see rejection of claim 18).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL CALRISSIAN PUENTES whose telephone number is (571)270-5070. The examiner can normally be reached M-F 9-6:30 (flex).
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/DANIEL C PUENTES/Primary Examiner, Art Unit 2849