DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract ideas without significantly more. The claims recite mental processes. This judicial exception is not integrated into a practical application because the claims generally link abstract ideas to a generic computer. The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because they include mere instructions to perform mental processes on a generic computer without creating a significant improvement or change to the computer.
Claim 1,
Step 2A Prong 1: Identification of Abstract Ideas
An apparatus comprising: a processor to process request transactions and completion transactions for one or more respective communication protocols; (MPEP 2106.04(a)(2)(III)(B) A Claim That Encompasses a Human Performing the Step(s) Mentally With or Without a Physical Aid Recites a Mental Process)
Step 2A Prong 2: Identification of Additional Elements
a processor(MPEP 2106.04(d): regarding, “simply implementing a mathematical principle on a physical machine, namely a computer, was not a patentable application of that principle”)
memory coupled to the processor (MPEP 2106.04(d): regarding, “simply implementing a mathematical principle on a physical machine, namely a computer, was not a patentable application of that principle”) to store error-related transaction information; (MPEP 2106.05(g): mere data gathering is an Insignificant Extra-Solution Activity)
and circuitry coupled to the memory (MPEP 2106.04(d): regarding, “simply implementing a mathematical principle on a physical machine, namely a computer, was not a patentable application of that principle”) to save the error-related transaction information in the memory for both the request transactions and the completion transactions for the one or more respective communication protocols. (MPEP 2106.05(g): mere data gathering is an Insignificant Extra-Solution Activity)
Step 2B: Significantly More Analysis
The additional elements of the claim do not integrate the abstract idea into a practical application. The additional elements amount to mere instructions to apply the judicial exceptions on a computer and insignificant extra-solution activity. (MPEG 2106.05(f))
Claim 2,
Claim 2 merely further describe the error-related transaction information of claim 1, respectively
Claim 3,
Claim 3 merely further describe the error-related transaction information of claim 1, respectively
Claim 4,
Step 2A Prong 2: Identification of Additional Elements
The apparatus of claim 1, wherein the memory comprises one or more configuration registers, (this merely further describe the memory of claim 1, respectively)
and wherein the circuitry is further to: save the error-related transaction information in the memory based on one or more respective values from the one or more configuration registers. (MPEP 2106.05(g): mere data gathering is an Insignificant Extra-Solution Activity)
Step 2B: Significantly More Analysis
The additional elements of the claim do not integrate the abstract idea into a practical application. The combination of these additional elements are no more than mere data gathering in conjunction with the abstract idea in order to provide data for the mental process to be applied to. (MPEG 2106.05(g))
Claim 5,
Step 2A Prong 2: Identification of Additional Elements
The apparatus of claim 1, wherein the circuitry is further to: save the error-related transaction information in the memory associated with two or more error severity levels. (MPEP 2106.05(g): mere data gathering is an Insignificant Extra-Solution Activity)
Step 2B: Significantly More Analysis
The additional elements of the claim do not integrate the abstract idea into a practical application. The combination of these additional elements are no more than mere data gathering in conjunction with the abstract idea in order to provide data for the mental process to be applied to. (MPEG 2106.05(g))
Claim 6,
Step 2A Prong 2: Identification of Additional Elements
The apparatus of claim 5, further comprising: two or more registers (MPEP 2106.04(d): regarding, “simply implementing a mathematical principle on a physical machine, namely a computer, was not a patentable application of that principle”) to store respective status information associated with two or more error severity levels. (MPEP 2106.05(g): mere data gathering is an Insignificant Extra-Solution Activity)
Step 2B: Significantly More Analysis
The additional elements of the claim do not integrate the abstract idea into a practical application. The additional elements amount to mere instructions to apply the judicial exceptions on a computer and insignificant extra-solution activity. (MPEG 2106.05(f))
Claim 7,
Claim 7 merely further describe the two or more error severity levels of claim 5, respectively
Claim 8,
Step 2A Prong 1: Identification of Abstract Ideas
An apparatus, comprising: a processor to process request transactions and completion transactions for one or more respective communication protocols; (MPEP 2106.04(a)(2)(III)(B) A Claim That Encompasses a Human Performing the Step(s) Mentally With or Without a Physical Aid Recites a Mental Process)
Step 2A Prong 2: Identification of Additional Elements
a processor(MPEP 2106.04(d): regarding, “simply implementing a mathematical principle on a physical machine, namely a computer, was not a patentable application of that principle”)
memory coupled to the processor (MPEP 2106.04(d): regarding, “simply implementing a mathematical principle on a physical machine, namely a computer, was not a patentable application of that principle”) to store error-related transaction information; (MPEP 2106.05(g): mere data gathering is an Insignificant Extra-Solution Activity)
and circuitry coupled to the memory (MPEP 2106.04(d): regarding, “simply implementing a mathematical principle on a physical machine, namely a computer, was not a patentable application of that principle”) to save the error-related transaction information in the memory associated with two or more error severity levels for the one or more respective communication protocols. (MPEP 2106.05(g): mere data gathering is an Insignificant Extra-Solution Activity)
Step 2B: Significantly More Analysis
The additional elements of the claim do not integrate the abstract idea into a practical application. The additional elements amount to mere instructions to apply the judicial exceptions on a computer and insignificant extra-solution activity. (MPEG 2106.05(f))
Claim 9,
Step 2A Prong 2: Identification of Additional Elements
The apparatus of claim 8, further comprising: two or more registers (MPEP 2106.04(d): regarding, “simply implementing a mathematical principle on a physical machine, namely a computer, was not a patentable application of that principle”) to store respective status information associated with two or more error severity levels. (MPEP 2106.05(g): mere data gathering is an Insignificant Extra-Solution Activity)
Step 2B: Significantly More Analysis
The additional elements of the claim do not integrate the abstract idea into a practical application. The additional elements amount to mere instructions to apply the judicial exceptions on a computer and insignificant extra-solution activity. (MPEG 2106.05(f))
Claim 10,
Claim 10 merely further describe the two or more error severity levels of claim 8, respectively
Claim 11,
Claim 11 merely further describe the error-related transaction information of claim 8, respectively
Claim 12,
Claim 12 merely further describe the error-related transaction information of claim 8, respectively
Claim 13,
Step 2A Prong 2: Identification of Additional Elements
The apparatus of claim 8, wherein the memory comprises one or more configuration registers, (this merely further describe the memory of claim 8, respectively)
and wherein the circuitry is further to: save the error-related transaction information in the memory based on one or more respective values from the one or more configuration registers. (MPEP 2106.05(g): mere data gathering is an Insignificant Extra-Solution Activity)
Step 2B: Significantly More Analysis
The additional elements of the claim do not integrate the abstract idea into a practical application. The combination of these additional elements are no more than mere data gathering in conjunction with the abstract idea in order to provide data for the mental process to be applied to. (MPEG 2106.05(g))
Claim 14,
Step 2A Prong 2: Identification of Additional Elements
The apparatus of claim 8, wherein the circuitry is further to: save the error-related transaction information in the memory for both the request transactions and the completion transactions for the one or more respective communication protocols. (MPEP 2106.05(g): mere data gathering is an Insignificant Extra-Solution Activity)
Step 2B: Significantly More Analysis
The additional elements of the claim do not integrate the abstract idea into a practical application. The combination of these additional elements are no more than mere data gathering in conjunction with the abstract idea in order to provide data for the mental to be applied to. (MPEG 2106.05(g))
Claim 15,
Step 2A Prong 1: Identification of Abstract Ideas
and error management circuitry to collect header log information from both request transactions and completion transactions for the one or more communication protocols. (MPEP 2106.04(a)(2)(III)(B) A Claim That Encompasses a Human Performing the Step(s) Mentally With or Without a Physical Aid Recites a Mental Process)
Step 2A Prong 2: Identification of Additional Elements
An electronic device, comprising: a processor; (MPEP 2106.04(d): regarding, “simply implementing a mathematical principle on a physical machine, namely a computer, was not a patentable application of that principle”)
interface circuitry coupled to the processor to support one or more communication protocols; (MPEP 2106.04(d): regarding, “simply implementing a mathematical principle on a physical machine, namely a computer, was not a patentable application of that principle”)
and error management circuitry (MPEP 2106.04(d): regarding, “simply implementing a mathematical principle on a physical machine, namely a computer, was not a patentable application of that principle”)
Step 2B: Significantly More Analysis
The additional elements of the claim do not integrate the abstract idea into a practical application. The additional elements amount to mere instructions to apply the judicial exceptions on a generic computer (MPEG 2106.05(f)). The computer is cited at such a high level of generality that it cannot be determined to be a particular machine (MPEP 2106.05(b)) and is simply linking the judicial exception to a particular technology (MPEP 2106.05(h))
Claim 16,
Step 2A Prong 2: Identification of Additional Elements
The electronic device of claim 15, wherein the error management circuitry comprises one or more configuration registers, (this merely further describe the error management circuitry of claim 15, respectively)
and wherein the error management circuitry is further to: collect the header log information based on one or more respective values from the one or more configuration registers. (MPEP 2106.05(g): mere data gathering is an Insignificant Extra-Solution Activity)
Step 2B: Significantly More Analysis
The additional elements of the claim do not integrate the abstract idea into a practical application. The combination of these additional elements are no more than mere data gathering in conjunction with the abstract idea in order to provide data for the mental process to be applied to. (MPEG 2106.05(g))
Claim 17,
Step 2A Prong 2: Identification of Additional Elements
The electronic device of claim 15, wherein the error management circuitry is further to: collect header log information associated with two or more error severity levels. (MPEP 2106.05(g): mere data gathering is an Insignificant Extra-Solution Activity)
Step 2B: Significantly More Analysis
The additional elements of the claim do not integrate the abstract idea into a practical application. The combination of these additional elements are no more than mere data gathering in conjunction with the abstract idea in order to provide data for the mental process to be applied to. (MPEG 2106.05(g))
Claim 18,
Step 2A Prong 2: Identification of Additional Elements
The electronic device of claim 15, wherein the error management circuitry is further to: collect header log information for both the request transactions and the completion transactions for two or more respective communication protocols. (MPEP 2106.05(g): mere data gathering is an Insignificant Extra-Solution Activity)
Step 2B: Significantly More Analysis
The additional elements of the claim do not integrate the abstract idea into a practical application. The combination of these additional elements are no more than mere data gathering in conjunction with the abstract idea in order to provide data for the mental process to be applied to. (MPEG 2106.05(g))
Claim 19,
Claim 19 merely further describe the two or more respective communication protocols of claim 18, respectively
Claim 20,
Claim 20 merely further describe the error management circuitry of claim 15, respectively
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 15-16, 18, 20 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Gong (US 20210271537 A1)
Regarding Claim 1, Gong teaches:
An apparatus comprising: a processor (Gong, Fig. 2, Processing Core) to process request transactions and completion transactions for one or more respective communication protocols; (Gong, Fig. 2, Processing Core <-> 205, [0032] The translation layer 205 typically manages credit-base flow control for TLPs. PCIe implements split transactions, i.e. transactions with request and response separated by time, allowing a link to carry other traffic while the target device gathers data for the response.)
memory coupled to the processor to store error-related transaction information; (Gong, Fig. 2, Processing Core <-> 205…222 <-> External Device, abstract, . The extension device further includes memory to store an event register, where the extension device is to write data to the event register to describe detection of an error by the error detection circuitry. )
and circuitry coupled to the memory to save the error-related transaction information in the memory for both the request transactions and the completion transactions for the one or more respective communication protocols. (Gong, [0028] Further, one or more links (e.g., 123) of the system can include one or more extension devices (e.g., 150), such as retimers, redrivers, repeaters, etc. [0111] Example 1 is an apparatus including: a retimer to extend a point-to-point link to connect two devices, where the retimer includes: error detection circuitry to detect a set of errors at the retimer; memory to store an event register, where the retimer is to write data to the event register to describe detection of an error by the error detection circuitry;)
Regarding Claim 2, Gong teaches:
The apparatus of claim 1, wherein the error-related transaction information at least includes header log information associated with a completion transaction. (Gong, [0032] The translation layer 205 typically manages credit-base flow control for TLPs. PCIe implements split transactions, i.e. transactions with request and response separated by time, allowing a link to carry other traffic while the target device gathers data for the response. [0042] One side of the Data Link Layer 210 accepts TLPs assembled by the Transaction Layer 205, applies packet sequence identifier 211, i.e. an identification number or packet number, calculates and applies an error detection code, i.e. CRC 212, and submits the modified TLPs to the Physical Layer 220 for transmission across a physical to an external device.)
Regarding Claim 3, Gong teaches:
The apparatus of claim 1, wherein the error-related transaction information at least includes header log information associated with a correctable error. (Gong, [0042] One side of the Data Link Layer 210 accepts TLPs assembled by the Transaction Layer 205, applies packet sequence identifier 211, i.e. an identification number or packet number, calculates and applies an error detection code, i.e. CRC 212, and submits the modified TLPs to the Physical Layer 220 for transmission across a physical to an external device. [0060] Upon detecting the presence of an event recorded in the internal event register of a retimer 710 (based on detection of the event by the retimer), a system controller may access and read the event register 735 to identify details concerning the event and, if possible or relevant, initiate corrective action to remedy the event. Examiner's note: corrective action is only initiated when the error event is eligible)
Regarding Claim 4, Gong teaches:
The apparatus of claim 1, wherein the memory comprises one or more configuration registers, (Gong, abstract, . The extension device further includes memory to store an event register )
and wherein the circuitry is further to: save the error-related transaction information in the memory based on one or more respective values from the one or more configuration registers. (Gong, [0057] As errors and other events are detected using error detection logic 730, the error detection logic 730 may record the event in one or more event registers 735 provided in internal computer memory of the retimer 710. Fig. 8A, 810, 815, [0065] As represented in FIGS. 8A-8B, an example events register may include sub-registers or fields dedicated to respective types of events. For example, physical layer errors (e.g., 810) may be one event type, internal retimer errors (e.g., 815) may be another event type, and so on. )
Regarding Claim 15, Gong teaches:
An electronic device, comprising: a processor; (Gong, Fig. 2, Processing Core)
interface circuitry coupled to the processor to support one or more communication protocols; (Gong, Fig. 1, 115)
and error management circuitry (Gong, Fig. 1, 125, Fig. 2, External Device) to collect header log information from both request transactions and completion transactions for the one or more communication protocols. (Gong, Fig. 2, 205…222 -> External Device, [0032] The translation layer 205 typically manages credit-base flow control for TLPs. PCIe implements split transactions, i.e. transactions with request and response separated by time, allowing a link to carry other traffic while the target device gathers data for the response.)
Regarding Claim 16, Gong teaches:
The electronic device of claim 15, wherein the error management circuitry (Gong, Fig. 1, 125, Fig. 2, External Device) comprises one or more configuration registers, (Gong, abstract, . The extension device further includes memory to store an event register )
and wherein the error management circuitry is further to: collect the header log information based on one or more respective values from the one or more configuration registers. (Gong, [0057] As errors and other events are detected using error detection logic 730, the error detection logic 730 may record the event in one or more event registers 735 provided in internal computer memory of the retimer 710. Fig. 8A, 810, 815, [0065] As represented in FIGS. 8A-8B, an example events register may include sub-registers or fields dedicated to respective types of events. For example, physical layer errors (e.g., 810) may be one event type, internal retimer errors (e.g., 815) may be another event type, and so on. )
Regarding Claim 18, Gong teaches:
The electronic device of claim 15, wherein the error management circuitry is further to: collect header log information for both the request transactions and the completion transactions for two or more respective communication protocols. (Gong, Fig. 2, 205…222 -> External Device, [0032] In one embodiment, transaction layer 205 is to provide an interface between a device's processing core and the interconnect architecture, such as data link layer 210 and physical layer 220...The translation layer 205 typically manages credit-base flow control for TLPs. PCIe implements split transactions, i.e. transactions with request and response separated by time, allowing a link to carry other traffic while the target device gathers data for the response. [0050] In some implementations, a link, such as a link compliant with PCIe, USB, UPI, or other interconnect protocol, can include one or more retimers or other extension devices, such as a redriver or repeater.)
Regarding Claim 20, Gong teaches:
The electronic device of claim 15, wherein the error management circuitry comprises a set of memory-mapped registers to store the collected header log information. (Gong, [0034] Memory space transactions include one or more of read requests and write requests to transfer data to/from a memory-mapped location.)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-14, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gong (US 20210271537 A1), in view of Wickeraad (US 7346812 B1)
Regarding Claim 5, Gong does not explicitly teach:
The apparatus of claim 1, wherein the circuitry is further to: save the error-related transaction information in the memory associated with two or more error severity levels.
However, Wickeraad teaches:
The apparatus of claim 1, wherein the circuitry is further to: save the error-related transaction information in the memory associated with two or more error severity levels. (Wickeraad, abstract, second embodiment of the invention involves a data processing system or an error log system, having an associated error level chosen from a plurality of error levels for an error. The data processing system or error log system includes a set of memory cells, with a primary error log to record the error, at least one error enable register that can be read and written to redefine the error level of the error to one of said plurality of error levels.)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Gong with error logging system with plurality of error levels as taught by Wickeraad, because many data processing systems (e.g., computer systems, programmable electronic systems, telecommunication switching systems, control systems, and so forth) detect different types of errors. Some errors indicate a minor problem while other errors indicate a serious problem. Because data processing systems are being designed to offer higher percentages of "up-time," it is critical to know how severe an error is and whether the system must be shut down to limit data corruption, or if the system can continue to operate without impact to the user. (Wickeraad, Col. 1, 12-21)
Regarding Claim 6, Gong in view of Wickeraad teaches:
The apparatus of claim 5, further comprising: two or more registers to store respective status information associated with two or more error severity levels. (Wickeraad, Fig. 3-5, Col. 2, line 24-32, FIG. 3 shows a third register that is used for fatal error enabling, which allows any error to be defined to be at the fatal error level. FIG. 4 shows a fourth register that is used for uncorrectable error enabling, which allows any error to be defined to be at the uncorrectable error level. FIG. 5 shows a fifth register that is used for correctable error enabling, which allows any error to be defined to be at the correctable error level.)
Regarding Claim 7, Gong in view of Wickeraad teaches:
The apparatus of claim 5, wherein the two or more error severity levels include at least a correctable error severity level and an uncorrectable error severity level. (Wickeraad, Fig. 4, 400; Fig. 5, 500)
Regarding Claim 8, Gong in view of Wickeraad teaches:
An apparatus, comprising: a processor (Gong, Fig. 2, Processing Core) to process request transactions and completion transactions for one or more respective communication protocols; (Gong, Fig. 2, Processing Core <-> 205, [0032] The translation layer 205 typically manages credit-base flow control for TLPs. PCIe implements split transactions, i.e. transactions with request and response separated by time, allowing a link to carry other traffic while the target device gathers data for the response.)
memory coupled to the processor to store error-related transaction information; (Gong, Fig. 2, Processing Core <-> 205…222 <-> External Device, abstract, . The extension device further includes memory to store an event register, where the extension device is to write data to the event register to describe detection of an error by the error detection circuitry. )
and circuitry coupled to the memory (Gong, [0111] … where the retimer includes: error detection circuitry to detect a set of errors at the retimer; memory to store an event register, where the retimer is to write data to the event register to describe detection of an error by the error detection circuitry;) to save the error-related transaction information in the memory associated with two or more error severity levels for the one or more respective communication protocols. (Wickeraad, abstract, second embodiment of the invention involves a data processing system or an error log system, having an associated error level chosen from a plurality of error levels for an error. The data processing system or error log system includes a set of memory cells, with a primary error log to record the error, at least one error enable register that can be read and written to redefine the error level of the error to one of said plurality of error levels. Gong [0032] PCIe implements split transactions, i.e. transactions with request and response separated by time, allowing a link to carry other traffic while the target device gathers data for the response.)
Regarding Claim 9, Gong in view of Wickeraad teaches:
The apparatus of claim 8, further comprising: two or more registers to store respective status information associated with two or more error severity levels. (Wickeraad, Fig. 3-5, Col. 2, line 24-32, FIG. 3 shows a third register that is used for fatal error enabling, which allows any error to be defined to be at the fatal error level. FIG. 4 shows a fourth register that is used for uncorrectable error enabling, which allows any error to be defined to be at the uncorrectable error level. FIG. 5 shows a fifth register that is used for correctable error enabling, which allows any error to be defined to be at the correctable error level.)
Regarding Claim 10, Gong in view of Wickeraad teaches:
The apparatus of claim 8, wherein the two or more error severity levels include at least a correctable error severity level and an uncorrectable error severity level. (Wickeraad, Fig. 4, 400; Fig. 5, 500)
Regarding Claim 11, Gong in view of Wickeraad teaches:
The apparatus of claim 8, wherein the error-related transaction information at least includes header log information associated with a completion transaction. (Gong, [0032] The translation layer 205 typically manages credit-base flow control for TLPs. PCIe implements split transactions, i.e. transactions with request and response separated by time, allowing a link to carry other traffic while the target device gathers data for the response. [0042] One side of the Data Link Layer 210 accepts TLPs assembled by the Transaction Layer 205, applies packet sequence identifier 211, i.e. an identification number or packet number, calculates and applies an error detection code, i.e. CRC 212, and submits the modified TLPs to the Physical Layer 220 for transmission across a physical to an external device.)
Regarding Claim 12, Gong in view of Wickeraad teaches:
The apparatus of claim 8, wherein the error-related transaction information at least includes header log information associated with a correctable error. (Gong, [0042] One side of the Data Link Layer 210 accepts TLPs assembled by the Transaction Layer 205, applies packet sequence identifier 211, i.e. an identification number or packet number, calculates and applies an error detection code, i.e. CRC 212, and submits the modified TLPs to the Physical Layer 220 for transmission across a physical to an external device. [0060] Upon detecting the presence of an event recorded in the internal event register of a retimer 710 (based on detection of the event by the retimer), a system controller may access and read the event register 735 to identify details concerning the event and, if possible or relevant, initiate corrective action to remedy the event. Examiner's note: corrective action is only initiated when the error event is eligible)
Regarding Claim 13, Gong in view of Wickeraad teaches:
The apparatus of claim 8, wherein the memory comprises one or more configuration registers, (Gong, abstract, . The extension device further includes memory to store an event register )
and wherein the circuitry is further to: save the error-related transaction information in the memory based on one or more respective values from the one or more configuration registers. (Gong, [0057] As errors and other events are detected using error detection logic 730, the error detection logic 730 may record the event in one or more event registers 735 provided in internal computer memory of the retimer 710. Fig. 8A, 810, 815, [0065] As represented in FIGS. 8A-8B, an example events register may include sub-registers or fields dedicated to respective types of events. For example, physical layer errors (e.g., 810) may be one event type, internal retimer errors (e.g., 815) may be another event type, and so on. )
Regarding Claim 14, Gong in view of Wickeraad teaches:
The apparatus of claim 8, wherein the circuitry is further to: save the error-related transaction information in the memory for both the request transactions and the completion transactions for the one or more respective communication protocols. (Gong, [0028] Further, one or more links (e.g., 123) of the system can include one or more extension devices (e.g., 150), such as retimers, redrivers, repeaters, etc. [0111] Example 1 is an apparatus including: a retimer to extend a point-to-point link to connect two devices, where the retimer includes: error detection circuitry to detect a set of errors at the retimer; memory to store an event register, where the retimer is to write data to the event register to describe detection of an error by the error detection circuitry;)
Regarding Claim 17, Gong in view of Wickeraad teaches:
The electronic device of claim 15, wherein the error management circuitry is further to: collect header log information associated with two or more error severity levels. (Gong, [0042] One side of the Data Link Layer 210 accepts TLPs assembled by the Transaction Layer 205, applies packet sequence identifier 211, i.e. an identification number or packet number, calculates and applies an error detection code, i.e. CRC 212, and submits the modified TLPs to the Physical Layer 220 for transmission across a physical to an external device. Wickeraad, abstract, second embodiment of the invention involves a data processing system or an error log system, having an associated error level chosen from a plurality of error levels for an error. The data processing system or error log system includes a set of memory cells, with a primary error log to record the error, at least one error enable register that can be read and written to redefine the error level of the error to one of said plurality of error levels.)
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gong (US 20210271537 A1), in view of Trantham (US 20230305972 A1)
Regarding Claim 19, Gong does not explicitly teach:
The electronic device of claim 18, wherein the two or more respective communication protocols include at least a Peripheral Component Interconnect Express (PCIe) protocol and a Compute Express Link (CXL) protocol.
However, Gong does teach:
([0050] In some implementations, a link, such as a link compliant with PCIe, USB, UPI, or other interconnect protocol, can include one or more retimers or other extension devices, such as a redriver or repeater.)
And Trantham teaches:
([0019] The memory module 102 and the microprocessor 120 can be communicatively coupled via an interface, such as Compute Express Link (CXL), Peripheral Component Interconnect Express (PCIe) interface, or another interface.)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Gong with CXL as taught by Trantham, because In some embodiments, the host interface 222 can be a PCIe interface utilizing the CXL protocol. (Trantham, [0026])
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hong (US 11720438 B2): teaches storing error data in registers in microprocessor (abstract)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XINYUAN YU whose telephone number is (571)272-7140. The examiner can normally be reached Monday-Friday 8:30-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bryce Bonzo can be reached at 571-272-3655. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/XINYUAN YU/Examiner, Art Unit 2113 /BRYCE P BONZO/Supervisory Patent Examiner, Art Unit 2113
