DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim(s) 9-10 and 18-19 is/are objected to because of the following informalities:
Claims 9-10 recite the limitation "the forward lithography estimator.” There is insufficient antecedent basis for this limitation in the claims. For the purposes of examination, the limitation is interpreted as “a forward lithography estimator.”
Claims 18-19 recite the limitation “the method.” There is insufficient antecedent basis for this limitation in the claims. For the purposes of examination, the limitation is interpreted as “the system.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1, 3, 6, 16, 20 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim(s) 1, 16, 20 recite(s) the limitations “an iteration” and “at least one iteration.” It is unclear if these iterations are the same or different, rendering the claim(s) indefinite. For the purposes of examination, “an iteration” and “at least one iteration” are interpreted to refer to the same single iteration.
Claim(s) 3 recite(s) the limitation “wherein a number of iterations included in the plurality of iterations is predefined.” It is unclear whether the number of iterations are the same type of iteration included in the plurality of iterations of claim 2 (i.e. are the iterations the same type), thereby rendering the claim(s) indefinite. For the purposes of examination, the limitation is interpreted to be “wherein a number of the plurality of iterations is predefined.”
Claim(s) 6 recite(s) the limitation “the iteration.” It is unclear which iteration the language is referring to the specific “an iteration” or the generic “at least one iteration” of the process in claim 1, thereby rendering the claim(s) indefinite. For the purposes of examination and in light of the aforementioned 112(b) interpretation of claim 1, “the iteration” is interpreted to refer to the same single iteration of “an iteration” and “at least one iteration.”
Claim(s) 16, 20 recite(s) the limitation “the iteration.” It is unclear which iteration the language is referring to the specific “an iteration” or the generic “at least one iteration” of the process in claim(s) 16, 20, thereby rendering the claim(s) indefinite. For the purposes of examination and in light of the aforementioned 112(b) interpretation of claims 16, 20, “the iteration” is interpreted to refer to the same single iteration of “an iteration” and “at least one iteration.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 11-12, 16, 19-20 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Poonawala (US 20210181620 A1).
Regarding claim 1, Poonawala teaches a method comprising: at a device, during an iteration of at least one iteration of an inverse lithography process (Poonawala, “using Inverse Lithography Technology (ILT),” [0006, 0036-0041]): processing an input mask image and an input design image (Poonawala, process input training mask and input design pattern/image, [0006, 0036-0041]), utilizing a machine learning model, to predict an output mask image (Poonawala, given these inputs, using “the ML [machine learning] model,” synthesize/predict a mask image, [0006, 0036-0041].; and outputting the output mask image (Poonawala, given these inputs, using “the ML [machine learning] model,” synthesize/predict and output mask image “for use in manufacturing,” [0006, 0036-0041]).
Regarding claim 11, Poonawala teaches the method of claim 1, wherein the inverse lithography process predicts an optimized mask image for the input design image (Poonawala, ILT process predicts a “lithographically optimized mask” for the input design, [0041-0047]).
Regarding claim 12, Poonawala teaches the method of claim 1, wherein the machine learning model is an implicit layer (Poonawala, Fig. 1a, machine learning model is an implicit layer, in that it models a joint condition of its input and output, learning optimization from training design-mask pairs and not by explicitly specifying the computation to arrive at a particular output, which is the definition of an implicit layer, [0006, 0036-0041]).
Regarding claims 16, 19-20, the rationale provided in the rejection of claims 1, 11 is incorporated herein. In addition, the system/method of claims 16, 19 (Poonawala, Fig. 11, machine-readable medium 1124, processor 1102, memory 1104, [0095-0100]) and the non-transitory computer-readable media of claim 20 (Poonawala, Fig. 11, machine-readable medium 1124, processor 1102, [0095-0100]) corresponds to the method of claims 1, 11, and performs the steps disclosed herein.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-4, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Poonawala as applied to claim 1 above, in view of Z. Yu, G. Chen, Y. Ma and B. Yu, "A GPU-enabled Level Set Method for Mask Optimization," 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, 2021, pp. 1835-1838, doi: 10.23919/DATE51398.2021.9474212., hereinafter referred to as Yu.
Regarding claim 2, Poonawala teaches the method of claim 1.
However, Poonawala fails to teach where Yu teaches wherein the inverse lithography process includes a plurality of iterations (Yu, Fig. 2, Algorithm 1, ILT process includes t (Fig. 2) or N (Algorithm 1) plurality of iterations, pgs. 3-4).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Poonawala using the teachings of Yu to include Yu’s plurality of iterations of an inverse lithography technology (ILT) process to Poonawala’s iteration of an ILT process. Doing so would improve the ILT process by providing a plurality of iterations, which would be used to further refine the mask output for improved optimization.
Regarding claim 3, the combination of Poonawala and Yu teaches the method of claim 2, wherein a number of iterations included in the plurality of iterations is predefined (Yu, Algorithm 1, number of iterations N is “pre-set,” pg. 4).
Regarding claim 4, the combination of Poonawala and Yu teaches the method of claim 2, wherein for an initial iteration of the inverse lithography process, the input mask image is an initialized mask image (Yu, Algorithm 1, input mask image M0 for initial iteration of ILT is “initialized,” pgs. 3-4).
Regarding claim 17, the rationale provided in the rejection of claim 2 is incorporated herein. In addition, the system of claim 17 (Poonawala, Fig. 11, machine-readable medium 1124, processor 1102, memory 1104, [0095-0100]) corresponds to the method of claim 2, and performs the steps disclosed herein.
Claim(s) 5, 18, is/are rejected under 35 U.S.C. 103 as being unpatentable over Poonawala in view of Yu as applied to claims 4, 17 above, further in view of Dhananjay (WO 2019066861 A1).
Regarding claim 5, the combination of Poonawala and Yu teaches the method of claim 4.
However, the combination of Poonawala and Yu fails to teach where Dhananjay teaches wherein for each subsequent iteration of the inverse lithography process the input mask image is the output mask image predicted during a prior iteration (Dhananjay, for an “inverse lithography output,” iterative optimization occurs “with each operation taking the output of the preceding operation as the input mask pattern,” pg. 41/64).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have further modified Poonawala, as modified by Yu, using the teachings of Dhananjay to include Dhananjay’s use of the prior output mask, including an ILT output, as the input mask for subsequent OPC operation iterations to Poonawala’s, as modified by Yu, input and output masks in ILT operation iterations. Doing so would improve ILT operation iterations by providing use of the prior output mask as the input mask, which would be used to more efficiently iteratively optimize the mask.
Regarding claim 18, the rationale provided in the rejection of claim 5 is incorporated herein. In addition, the system/method of claim 18 (Poonawala, Fig. 11, machine-readable medium 1124, processor 1102, memory 1104, [0095-0100]) corresponds to the method of claim 5, and performs the steps disclosed herein.
Claim(s) 6-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Poonawala as applied to claim 1 above, in view of Liu, P., "Mask synthesis using machine learning software and hardware platforms," Proc. SPIE 11327, Optical Microlithography XXXIII, 1132707 (23 March 2020); https://doi.org/10.1117/12.2551816., hereinafter referred to as Liu.
Regarding claim 6, Poonawala teaches the method of claim 1.
However, Poonawala fails to teach where Liu teaches wherein during the iteration, the machine learning model further processes an input resist image (Liu, Fig. 1, machine learning model further processes, in addition to an input mask image, an input resist image, pgs. 3, 6-7).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Poonawala using the teachings of Liu to include Liu’s machine learning model’s processing of an input resist image and input mask image to Poonawala’s machine learning processing of an input mask image and input design pattern. Doing so would improve machine learning processing for mask synthesis by providing an input resist image, which would be used to more fully characterize and optimize the output mask.
Regarding claim 7, the combination of Poonawala and Liu teaches the method of claim 6, wherein the input resist image is generated as a function of the input mask image (Liu, Fig. 1, input resist image is generated as a function of the input mask image/layout, pgs. 3-6).
Regarding claim 8, the combination of Poonawala and Liu teaches the method of claim 6, wherein the input resist image is generated by a forward lithography estimator (Liu, Fig. 1, input resist image is generated by a forward lithography estimator in “the lithography system…forward simulation flow to predict the resist image,” pg. 3, 6-7).
Regarding claim 9, the combination of Poonawala and Liu teaches the method of claim 6 wherein the forward lithography estimator is a second machine learning model (Liu, Figs. 1, 6, the forward lithography estimator/flow simulation is another/second machine learning model, pgs. 3-6) or an existing physics model.
Regarding claim 10, the combination of Poonawala and Liu teaches the method of claim 6, wherein the forward lithography estimator is a pretrained function (Liu, Fig. 6, forward lithography estimator is pretrained, pgs. 3-6).
Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Poonawala as applied to claim 1 above, in view of B. Jiang, L. Liu, Y. Ma, H. Zhang, B. Yu and E. F. Y. Young, "Neural-ILT: Migrating ILT to Neural Networks for Mask Printability and Complexity Co-optimization," 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), San Diego, CA, USA, 2020, pp. 1-9., hereinafter referred to Jiang.
Regarding claim 13, Poonawala teaches the method of claim 1.
However, Poonawala fails to teach where Jiang teaches wherein the machine learning model is trained using a predefined number of iterations (Jiang, Fig. 7, ILT machine learning model is trained using a predefined number of iterations, pgs. 8-9).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Poonawala using the teachings of Jiang to include Jiang’s training of the ILT machine learning model using a predefined number of iterations to Poonawala’s training of the ILT machine learning model. Doing so would improve training of the ILT machine learning model by providing a predefined number of iterations, which would be used to conserve processing power by limiting the power spent on training.
Regarding claim 14, the combination of Poonawala and Jiang teaches the method of claim 13, wherein the machine learning model is trained using back- propagation through the predefined number of iterations (Jiang, Fig. 2, machine learning model is trained using backward propagation through the predefined number of iterations, pgs. 4-7).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Poonawala in view of Jiang as applied to claim 13 above, further in view of H. Yang, S. Li, Y. Ma, B. Yu and E. F. Y. Young, "GAN-OPC: Mask Optimization with Lithography-guided Generative Adversarial Nets," 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, 2018, pp. 1-6, doi: 10.1109/DAC.2018.8465816., hereinafter referred to as Yang.
Regarding claim 15, the combination of Poonawala and Jiang teaches the method of claim 13.
However, the combination of Poonawala and Jiang fails to teach where Yang teaches wherein the machine learning model is trained using a ground truth optimized mask (Yang, Algorithm 1, machine learning model is trained using ground truth optimized mask, pgs. 4-5).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have further modified Poonawala, as modified by Jiang, using the teachings of Yang to include Yang’s training of the machine learning model using a ground truth optimized mask to Poonawala’s, as modified by Jiang, training of the machine learning model. Doing so would improve training of the machine learning model by providing a ground truth optimized mask, which would be used to more efficiently and properly train the machine learning model.
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Poonawala in view of Yu and Dhananjay.
Regarding claim 21, Poonawala teaches a method of manufacturing a semiconductor device according to an original design image, the method comprising: receiving the original design image (Poonawala, Fig. 1a, receive original design image/pattern, [0006, 0036-0041]); defining a mask image for the original design image (Poonawala, Fig. 1a, define/produce a mask image for the original design image/pattern, [0006, 0036-0041]); providing the mask image and the original design image as an initial input to an inverse lithography machine learning model (Poonawala, Fig. 1a, provide the mask image and original design image as initial inputs to an inverse lithography machine learning model, [0006, 0036-0041]); iterating the steps of: the inverse lithography machine learning model generating from its current input a current output mask image that is optimized to the original design image (Poonawala, Figs. 1a, 8, ILT model generates from the inputs an output mask that is optimized to the original design image/pattern [0006, 0036-0041]), and the inverse lithography machine learning model outputting the current output mask image (Poonawala, Figs. 1a, 8, ILT model generates from the inputs an output mask that is optimized to the original design image/pattern [0006, 0036-0041]); and using a final current output mask image to perform lithography in physically manufacturing the semiconductor device (Poonawala, final output mask image is used to perform lithography in physically manufacturing the semiconductor device, [0006-0008, 0085]).
However, Poonawala fails to teach where Yu teaches at least two times iterating the steps of (Yu, Fig. 2, Algorithm 1, ILT process includes t (Fig. 2) or N (Algorithm 1) plurality (at least 2) of iterations, pgs. 3-4): the inverse lithography model generating from its current input a current output mask image that is optimized to the original design image (Yu, Fig. 2, Algorithm 1, ILT model generates from its current input an output mask image that is optimized to the original design image R,* pgs. 3-4), and the inverse lithography model outputting the current output mask image (Yu, Fig. 2, ILT model outputs the current output mask image, pgs. 3-4).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Poonawala using the teachings of Yu to include Yu’s plurality of iterations of an inverse lithography technology (ILT) process to Poonawala’s iteration of an ILT process with machine learning. Doing so would improve the ILT process by providing a plurality of iterations, which would be used to further refine the mask output for improved optimization.
However, the combination of Poonawala and Yu fails to teach where Dhananjay teaches a wherein for each iteration of the steps prior to a final iteration of the steps, the current output mask image is output for use along with the original design image as a next input to the inverse lithography machine learning model (Dhananjay, for each iteration, including for an “inverse lithography output,” iterative optimization occurs “with each operation taking the output of the preceding operation as the input mask pattern,” along with an association dataset that comprises the original target pattern and evaluation points “corresponding to the same…wafer target pattern” [corresponding to original design image] for “the iterative improvement of the quality of the predicted lithography outcome”, pgs. 41-43, 52/64, wherein Poonawala, as modified by Yu, discloses the model being an inverse lithography machine learning model).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have further modified Poonawala, as modified by Yu, using the teachings of Dhananjay to include Dhananjay’s use of the prior output mask, including an ILT output, as the input, alongside association dataset comprising target/original design image information for subsequent OPC operation iterations to Poonawala’s, as modified by Yu, input and output masks, along with target/original design images, in ILT operation iterations. Doing so would improve ILT operation iterations by providing use of the prior output mask as the input mask, which would be used to more efficiently iteratively optimize the mask.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEELY G YEARGIN whose telephone number is (571)272-5126. The examiner can normally be reached M-Th 8am-6pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Vincent Rudolph can be reached at (571) 272-8243. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KEELY GWYNNE YEARGIN/Examiner, Art Unit 2671
/VINCENT RUDOLPH/Supervisory Patent Examiner, Art Unit 2671
