DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 – 6, 12 – 16, and 20 – 32 are pending.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 25 and 28 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 2 of U.S. Patent No. 12,555,646. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the patent require all the limitations of the claims of the instant application.
Allowable Subject Matter
Claims 1 – 6, 12 – 16, and 20 – 24 are allowable.
Claims 25 – 32 would be allowable if rewritten, amended, or a proper terminal disclaimer is filed to overcome the non-statutory double patenting rejection(s) of claims 25 and 28 set forth in this office action.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 1 – 6, 23, and 24 are allowable because the prior art of record fails to teach or suggest alone or in combination the hardware interface to receive a first assertion and a second assertion of a chip select signal through the chip select input to trigger entry into a configuration register update mode; a decision feedback equalization (DFE) configuration register to store a first configuration setting for the hardware interface to the CA bus; and a second configuration register for a configuration setting other than DFE, the second configuration register to store a second configuration setting for the hardware interface to the CA bus; wherein the apparatus is to update the second configuration register with in-band register writes in the configuration register update mode, as required by independent claim 1, in combination with the other claimed limitations (emphasis added). US Patent Application Publication No. 2022/0300197 (hereinafter Sethuramin) teaches a memory device including registers which provide settings for operation of the memory device (Sethuramin; Paragraph [0031]) that includes storing training feedback (Sethuramin; Paragraphs [0042], [0052], and [0067]), but does not teach using specific in-band register writes to update a second configuration register other than the DFE configuration register, as required by independent claim 1. US Patent No. 11,675,728 (hereinafter Leslie) teaches a memory device including receiving and updating multiple configuration data through a command and address bus, including DFE parameters (Leslie; Col 2 Lines 1 – 11), but does not teach doing so utilizing in-band register writes in a configuration register update mode, as required by independent claim 1. US Patent No. 11,675,716 (hereinafter Mozak) teaches a memory device which receives a signal through a command/address bus to trigger entry into a configuration mode (Mozak; Abstract), but does not teach performing an update to a second configuration register with in-band register writes in the configuration register update mode, as required by independent claim 1.
Claims 2 – 6, 23, and 24 are also allowable because of their dependence, either directly or indirectly, upon allowable independent claim 1.
Claims 12 – 16 and 20 – 22 are allowable because the prior art of record fails to teach or suggest alone or in combination the memory chip to receive from the memory controller a first assertion and a second assertion of a chip select signal through the chip select input to trigger the memory chip to enter a configuration register update mode, the memory chip including: a decision feedback equalization (DFE) configuration register to store a first configuration setting for the CA bus interface; and a second configuration register for a configuration setting other than DFE, the second configuration register to store a second configuration setting for the CA bus interface; and wherein the memory chip is to update the second configuration register with in- band register writes in the configuration register update mode, as required by independent claim 12, in combination with the other claimed limitations (emphasis added). US Patent Application Publication No. 2022/0300197 (hereinafter Sethuramin) teaches a memory device including registers which provide settings for operation of the memory device (Sethuramin; Paragraph [0031]) that includes storing training feedback (Sethuramin; Paragraphs [0042], [0052], and [0067]), but does not teach using specific in-band register writes to update a second configuration register other than the DFE configuration register, as required by independent claim 12. US Patent No. 11,675,728 (hereinafter Leslie) teaches a memory device including receiving and updating multiple configuration data through a command and address bus, including DFE parameters (Leslie; Col 2 Lines 1 – 11), but does not teach doing so utilizing in-band register writes in a configuration register update mode, as required by independent claim 12. US Patent No. 11,675,716 (hereinafter Mozak) teaches a memory device which receives a signal through a command/address bus to trigger entry into a configuration mode (Mozak; Abstract), but does not teach performing an update to a second configuration register with in-band register writes in the configuration register update mode, as required by independent claim 12.
Claims 13 – 16 and 20 – 22 are also allowable because of their dependence, either directly or indirectly, upon allowable independent claim 12.
Claims 25 – 32 would be allowable if rewritten, amended, or a proper terminal disclaimer is filed to overcome the non-statutory double patenting rejection(s) of claims 25 and 28 set forth in this office action because the prior art of record fails to teach or suggest alone or in combination the hardware interface to receive a configuration register update mode command to trigger entry into a configuration register update mode; a decision feedback equalization (DFE) configuration register to store a first configuration setting for the hardware interface to the CA bus; and a second configuration register for a configuration setting other than DFE, the second configuration register to store a second configuration setting for the hardware interface to the CA bus; wherein the apparatus is to update the second configuration register with in-band register writes in the configuration register update mode, as required by independent claim 25, in combination with the other claimed limitations (emphasis added). US Patent Application Publication No. 2022/0300197 (hereinafter Sethuramin) teaches a memory device including registers which provide settings for operation of the memory device (Sethuramin; Paragraph [0031]) that includes storing training feedback (Sethuramin; Paragraphs [0042], [0052], and [0067]), but does not teach using specific in-band register writes to update a second configuration register other than the DFE configuration register, as required by independent claim 25. US Patent No. 11,675,728 (hereinafter Leslie) teaches a memory device including receiving and updating multiple configuration data through a command and address bus, including DFE parameters (Leslie; Col 2 Lines 1 – 11), but does not teach doing so utilizing in-band register writes in a configuration register update mode, as required by independent claim 25. US Patent No. 11,675,716 (hereinafter Mozak) teaches a memory device which receives a signal through a command/address bus to trigger entry into a configuration mode (Mozak; Abstract), but does not teach performing an update to a second configuration register with in-band register writes in the configuration register update mode, as required by independent claim 25.
Claims 26 – 32 would also be allowable because of their dependence, either directly or indirectly, upon allowable independent claim 25.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD B FRANKLIN whose telephone number is (571)272-0669. The examiner can normally be reached M-F 8:30am-5pm.
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/RICHARD B FRANKLIN/ Examiner, Art Unit 2181
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