DETAILED ACTION
Claims 1 through 10 originally filed 11 August 2023. By amendment received 12 June 2026; claims 1 through 9 are amended and claim 10 is cancelled. Claims 1 through 9 are addressed by this action.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments have been fully considered; they are addressed below.
Applicant argues that the drawing objection relating to reference character "150" is incorrect on the basis that the element referred to in Figure 1 is the same element referred to in subsequent figures. This explanation resolves the objection and the corresponding objection is withdrawn.
Applicant argues that all remaining drawing objections are resolved by the amendments to the specification. This argument is persuasive and the corresponding objections are withdrawn.
Applicant argues that the objections to the specification are resolved by the amendments to the specification. The present amendments resolve most of the specification objections. However, the specification retains the phrase "Referring to FIGS. 5 to 7" in ¶78. This phrase should be changed to "Referring to FIGS. 5A to 7" because there is no such Figure 5. Accordingly, this objection is maintained as set forth below and all other specification objections are withdrawn.
Applicant argues that the amendments to claims 2 and 3 overcome the previous rejections under 35 U.S.C. 112(d). This argument is persuasive and the corresponding rejections are withdrawn.
Applicant has amended claims 1 and 7 to require "[The isolator] to prevent the first and second power lines from being exposed to external environment". The previous combination set forth in rejecting these claims does not teach this feature. As such, the previous rejections are withdrawn. However, upon further search and consideration, Yu et al. (Yu, US Pub. 2020/0014169) has been located which, in combination with the previously cited art, renders this feature obvious to one of ordinary skill in the art. As such, new rejections have been formulated as set forth below.
Applicant argues that the combined teachings of Matsubara et al. (Matsubara, US Pub. 2016/0141839), Tsuji (US Pub. 2019/0067899), and Laflaquiere et al. (Laflaquiere, US Pub. 2019/0363520) do not teach or render obvious the limitation "Wherein the isolator is implemented as a component having adhesive properties; a micro VCSEL chip disposed and fixed on the isolator" ,as required by representative claim 1, because, according to applicant, Laflaquiere does not teach this feature. To support this argument, applicant contends that Laflaquiere employs a separate layer for bonding.
Initially, due to the above noted change in rejection, this argument is addressed as it applies to the present rejection on the basis of the combined teachings of Matsubara, Tsuji, Laflaquiere, and Yu.
Applicant's argument is not persuasive because the process described by Laflaquiere involves bonding to the layer cited in the rejection. Specifically, Laflaquiere states that the VCSEL is bonded to the silicon wafer by oxide bonding process to the SiO2 layer (Laflaquiere, ¶48 describing bonding of the VCSEL to layer 92 depicted in Figure 6). This bonding process of Laflaquiere produces a SiO2-SiO2 bond between the VCSEL and the SiO2 layer atop the silicon wafer which necessarily involves adhesion between the two SiO2 layers involved. Since the SiO2 layer of Laflaquiere that is cited in the rejection is the layer stated to be bonded to by an oxide bonding process, the cited SiO2 layer necessarily has adhesive properties. As such, this argument is not persuasive.
The limitation "Wherein the isolator is implemented as a component having adhesive properties; a micro VCSEL chip disposed and fixed on the isolator" is rendered obvious by the combined teachings of Matsubara, Tsuji, Laflaquiere, and Yu (see below). Applicant's argument that Laflaquiere does not teach this feature is not persuasive because the process described by Laflaquiere involves bonding to the layer cited in the rejection.
Applicant argues that the combined teachings of Matsubara, Tsuji, and Laflaquiere do not teach or render obvious the limitation "A first inter connector and a second inter connector electrically connecting the first power line and the second power line to a first metal layer and a second metal layer within the micro VCSEL chip, respectively, via etched portions of the isolator" ,as required by representative claim 1, because, according to applicant, Laflaquiere does not teach this feature. To support this argument, applicant contends that Laflaquiere performs electrical connection between the VCSEL and the substrate using vias.
Initially, due to the above noted change in rejection, this argument is addressed as it applies to the present rejection on the basis of the combined teachings of Matsubara, Tsuji, Laflaquiere, and Yu.
Applicant's argument is not persuasive because the formation of the vias of Laflaquiere necessarily involves etching the described isolator. Specifically, Laflaquiere states that connection between the VCSEL and the underlying silicon through vias formed down to the underlying silicon (Laflaquiere, ¶47 describing the connection lines 78 and 84 connected to terminals 68 and 86 as depicted in Figure 6). The connections of Laflaquiere from the VCSEL to the underlying silicon pass through the isolation layer (Laflaquiere, ¶48 describing the arrangement of isolation layer 92 as depicted in Figure 6). The vias of Laflaquiere are formed by etching (Laflaquiere, ¶45 generally describing the production of vias). Since the connections of Laflaquiere must penetrate the isolation layer thereof, since Laflaquiere states that such penetration of the isolation layer should be done by vias, and since vias are stated to be formed by etching layers that the vias penetrate, Laflaquiere necessarily teaches providing the necessary connections through etched portions of the isolator layer. As such, this argument is not persuasive.
The limitation "A first inter connector and a second inter connector electrically connecting the first power line and the second power line to a first metal layer and a second metal layer within the micro VCSEL chip, respectively, via etched portions of the isolator" is rendered obvious by the combined teachings of Matsubara, Tsuji, Laflaquiere, and Yu (see below). Applicant's argument that Laflaquiere does not teach this feature is not persuasive because the formation of the vias of Laflaquiere necessarily involves etching the described isolator.
As such, all claims are addressed as follows:
Specification
The specification is objected to under 37 C.F.R. 1.74. The specification refers to Figure 5 in ¶78 which is not used in the drawings. It is improper to use constructions such as "Fig. 1" to refer jointly to drawings that are labeled "Fig. 1A" and "Fig. 1B" (see MPEP 608.01f). The phrase "Referring to FIGS. 5 to 7" in ¶78 should be reworded as "Referring to FIGS. 5A to 7" or similar. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 3, this claim requires "Wherein the micro VCSEL chip is implemented as a cross section of a circular shape with one portion open." However, it is unclear what is meant by the phrase "a circular shape with one portion open" in the context of the "micro VCSEL chip" since it is unclear what would constitute a "portion" of a "circular shape" being "open" in the context of an entire VCSEL chip. While the original disclosure uses the exact phrase "a predetermined shape (circular shape) with one portion open", this phrase is used in relation to a metal layer that is formed as a circular ring and in which an opening in the ring may be readily understood (¶95 of the pre-grant publication of the original disclosure describing the shape of layer 270 in Figure 8B). It is unclear how the circular shape of a "micro VCSEL chip" could include "one portion open" in the same manner as with the disclosed metal layer since the disclosed metal layer is in the shape of a ring such that a missing portion of the ring would render the ring open whereas the disclosed chip is in the shape of a disk and it is not clear how a disk may be "open". As such, this claim is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. For the remainder of this action, this claim will be interpreted as meaning that the circular chip includes a metal layer that has an opening along the circle of the chip.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Matsubara et al. (Matsubara, US Pub. 2016/0141839), in view of Tsuji (US Pub. 2019/0067899), in view of Laflaquiere et al. (Laflaquiere, US Pub. 2019/0363520), and further in view of Yu et al. (Yu, US Pub. 2020/0014169).
Regarding claim 1, Matsubara discloses, "Wherein the micro VCSEL chip comprises a first reflector" (p. [0078] and Fig. 4, pt. 17). "[The first reflector] including a plurality of distributed Bragg reflector (DBR) pairs" (p. [0078] and Fig. 4, pt. 17). "A second reflector including a plurality of DBR pairs" (p. [0071] and Fig. 4, pt. 13). "A multiple quantum well layers positioned between the first reflector and the second reflector" (p. [0073] and Fig. 4, pts. 13, 15, and 17). "[The multiple quantum well layers] recombining holes generated from one of the first reflector and the second reflector and electrons generated from the other of the first reflector and the second reflector" (p. [0082] and Fig. 4, pts. 13, 15, 17, and 150). "A contact layer formed within one DBR pair of the second reflector or formed to contact the second reflector" (p. [0069] and Fig. 4, pts. 12 and 13). "A passivation layer protecting the first reflector, the second reflector, the multiple quantum well layers, and the contact layer from an outside" (p. [0088] and Fig. 4, pts. 12, 13, 15, 17, and 31). Matsubara does not explicitly disclose, "The first metal layer contacting the first reflector and supplying power to the first reflector." "The second metal layer contacting the contact layer and supplying power to the second reflector." Tsuji discloses, "The first metal layer contacting the first reflector and supplying power to the first reflector" (p. [0071], [0074], and Fig. 1, pts. 6 and 8). "The second metal layer contacting the contact layer and supplying power to the second reflector" (p. [0064], [0075], and Fig. 1, pts. 3 and 9). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Matsubara with the teachings of Tsuji. In view of the teachings of Matsubara regarding a VCSEL having ohmic contacts, the particular construction of the contacts of metal as taught by Tsuji would enhance the teachings of Matsubara by indicating suitable materials from which to form the electrodes.
The combination of Matsubara and Tsuji does not explicitly disclose, "A substrate." "First and second power lines formed on the substrate." "An isolator… coated on the substrate." "[The isolator] partially etched." "Wherein the isolator is implemented as a component having adhesive properties." "A micro VCSEL chip disposed and fixed on the isolator." "A first inter connector and a second inter connector electrically connecting the first power line and the second power line to a first metal layer and a second metal layer within the micro VCSEL chip, respectively." "[The first inter connector and the second inter connector connected] via etched portions of the isolator." "Wherein upper portions of the isolator are etched so that the first power line and the second power line are electrically connected with the first inter connector and the second inter connector, respectively." "The upper portions are positioned over the first power line and the second power line." Laflaquiere discloses, "A substrate" (p. [0038], [0041], and Figs. 3A and 3C, pts. 26 and 30). "First and second power lines formed on the substrate" (p. [0045], [0047], and Fig. 6, pts. 30, 68, and 86). "An isolator… coated on the substrate" (p. [0048] and Fig. 6, pts. 30 and 92). "[The isolator] partially etched" (p. [0045], [0048], and Fig. 6, pts. 68 and 92, where the vias through layer 92 are formed by partially etching layer 92). "Wherein the isolator is implemented as a component having adhesive properties" (p. [0048] and Fig. 6, pts. 32 and 92, where bonding the laser to layer 92 through an oxide bonding process requires layer 92 to have adhesive properties in the context of this process). "A micro VCSEL chip disposed and fixed on the isolator" (p. [0048] and Fig. 6, pts. 32 and 92). "A first inter connector and a second inter connector electrically connecting the first power line and the second power line to a first metal layer and a second metal layer within the micro VCSEL chip, respectively" (p. [0047] and Fig. 6, pts. 68, 78, 84, and 86). "[The first inter connector and the second inter connector connected] via etched portions of the isolator" (p. [0045], [0047], [0048], and Fig. 6, pts. 78, 84, and 92). "Wherein upper portions of the isolator are etched so that the first power line and the second power line are electrically connected with the first inter connector and the second inter connector, respectively" (p. [0045], [0047], [0048], and Fig. 6, pts. 68, 78, 84, 86, and 92). "The upper portions are positioned over the first power line and the second power line" (p. [0047], [0048], and Fig. 6, pts. 68, 86, and 92). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Matsubara and Tsuji with the teachings of Laflaquiere. In view of the teachings of Matsubara regarding a VCSEL chip, the additional inclusion of a circuit chip to which the laser devices are mounted as taught by Laflaquiere would enhance the teachings of Matsubara and Tsuji by allowing the laser devices to be integrated atop control circuitry.
The combination of Matsubara, Tsuji, and Laflaquiere does not explicitly disclose, "[The isolator] to prevent the first and second power lines from being exposed to external environment." Yu discloses, "[The isolator] to prevent the first and second power lines from being exposed to external environment" (p. [0029] and Fig. 8, pts. 204B and 206). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Matsubara, Tsuji, and Laflaquiere with the teachings of Yu. In view of the teachings of Matsubara regarding a VCSEL chip and the teachings of Laflaquiere regarding the inclusion of a circuit chip to which the laser devices are mounted, the alternate construction of the underlying circuit chip such that the power lines therein are directly covered by the upper insulation layer as taught by Yu would enhance the teachings of Matsubara, Tsuji, and Laflaquiere by allowing the depth of the power lines to be minimized.
Regarding claim 6, Matsubara discloses, "Wherein an area of the second metal layer is larger than or equal to that of the first metal layer" (Fig. 2, pts. 42 and 52).
Claims 2, 3, and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Matsubara, in view of Tsuji, in view of Laflaquiere, in view of Yu, and further in view of Roucka (US Pub. 2021/0305782).
Regarding claim 2, The combination of Matsubara, Tsuji, Laflaquiere, and Yu does not explicitly disclose, "Wherein the micro VCSEL chip is implemented as a cross section of a circular shape." Roucka discloses, "Wherein the micro VCSEL chip is implemented as a cross section of a circular shape" (p. [0082] and Figs. 19 and 20, where the chip is circular). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Matsubara, Tsuji, Laflaquiere, and Yu with the teachings of Roucka. In view of the teachings of Matsubara regarding a VCSEL chip, the alternate construction of the chip to have a circular shape as taught by Roucka would enhance the teachings of Matsubara, Tsuji, Laflaquiere, and Yu by providing a suitably alternate format in which to embody the VCSEL chip.
Regarding claim 3, The combination of Matsubara, Tsuji, Laflaquiere, and Yu does not explicitly disclose, "Wherein the micro VCSEL chip is implemented as a cross section of a circular shape with one portion open." Roucka discloses, "Wherein the micro VCSEL chip is implemented as a cross section of a circular shape with one portion open" (p. [0082] and Figs. 19 and 20, pt. 930). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Matsubara, Tsuji, Laflaquiere, and Yu with the teachings of Roucka for the reasons provided above regarding claim 2.
Regarding claim 5, Matsubara discloses, "Wherein an area of the first metal layer is larger than that of an opening" (Fig. 4, pts. 31 and 42).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Matsubara, in view of Tsuji, in view of Laflaquiere, in view of Yu, and further in view of Burroughs et al. (Burroughs, US Pub. 2018/0301875).
Regarding claim 4, The combination of Matsubara, Tsuji, Laflaquiere, and Yu does not explicitly disclose, "Wherein the contact layer has a mesa structure only on one side of the micro VCSEL chip." Burroughs discloses, "Wherein the contact layer has a mesa structure only on one side of the micro VCSEL chip" (Fig. 2B, pts. 200 and 206). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Matsubara, Tsuji, Laflaquiere, and Yu with the teachings of Burroughs. In view of the teachings of Matsubara regarding a VCSEL having a current spreading layer, the alternate construction of the current spreading layer to extend only to one side of the mesa as taught by Burroughs would enhance the teachings of Matsubara, Tsuji, Laflaquiere, and Yu by allowing the footprint of the device to be reduced.
Claims 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Matsubara, in view of Tsuji, in view of Laflaquiere, in view of Yu, and further in view of Kim (US Pub. 2006/0140235).
Regarding claim 7, Matsubara discloses, "Wherein the micro VCSEL chip comprises a first reflector" (p. [0078] and Fig. 4, pt. 17). "[The first reflector] including a plurality of distributed Bragg reflector (DBR) pairs" (p. [0078] and Fig. 4, pt. 17). "A second reflector including a plurality of DBR pairs" (p. [0071] and Fig. 4, pt. 13). "A plurality of multiple quantum well layers positioned between the first reflector and the second reflector" (p. [0073] and Fig. 4, pts. 13, 15, and 17). "[The plurality of multiple quantum well layers] recombining holes generated from one of the first reflector and the second reflector and electrons generated from the other of the first reflector and the second reflector" (p. [0082] and Fig. 4, pts. 13, 15, 17, and 150). "A contact layer formed within one DBR pair of the second reflector or formed to contact the second reflector" (p. [0069] and Fig. 4, pts. 12 and 13). "A passivation layer protecting the first reflector, the second reflector, the multiple quantum well layers, and the contact layer from an outside" (p. [0088] and Fig. 4, pts. 12, 13, 15, 17, and 31). Matsubara does not explicitly disclose, "The first metal layer contacting the first reflector and supplying power to the first reflector." "The second metal layer contacting the contact layer and supplying power to the second reflector." Tsuji discloses, "The first metal layer contacting the first reflector and supplying power to the first reflector" (p. [0071], [0074], and Fig. 1, pts. 6 and 8). "The second metal layer contacting the contact layer and supplying power to the second reflector" (p. [0064], [0075], and Fig. 1, pts. 3 and 9). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Matsubara with the teachings of Tsuji for the reasons provided above regarding claim 1.
The combination of Matsubara and Tsuji does not explicitly disclose, "A substrate." "First and second power lines formed on the substrate." "An isolator… coated on the substrate." "[The isolator] partially etched." "Wherein the isolator is implemented as a component having adhesive properties." "A micro VCSEL chip disposed and fixed on the isolator." "A first inter connector and a second inter connector electrically connecting the first power line and the second power line to a first metal layer and a second metal layer within the micro VCSEL chip, respectively." "[The first inter connector and the second inter connector connected] via etched portions of the isolator." "Wherein upper portions of the isolator are etched so that the first power line and the second power line are electrically connected with the first inter connector and the second inter connector, respectively." "The upper portions are positioned over the first power line and the second power line." Laflaquiere discloses, "A substrate" (p. [0038], [0041], and Figs. 3A and 3C, pts. 26 and 30). "First and second power lines formed on the substrate" (p. [0045], [0047], and Fig. 6, pts. 30, 68, and 86). "An isolator… coated on the substrate" (p. [0048] and Fig. 6, pts. 30 and 92). "[The isolator] partially etched" (p. [0045], [0048], and Fig. 6, pts. 68 and 92, where the vias through layer 92 are formed by partially etching layer 92). "Wherein the isolator is implemented as a component having adhesive properties" (p. [0048] and Fig. 6, pts. 32 and 92, where bonding the laser to layer 92 through an oxide bonding process requires layer 92 to have adhesive properties in the context of this process). "A micro VCSEL chip disposed and fixed on the isolator" (p. [0048] and Fig. 6, pts. 32 and 92). "A first inter connector and a second inter connector electrically connecting the first power line and the second power line to a first metal layer and a second metal layer within the micro VCSEL chip, respectively" (p. [0047] and Fig. 6, pts. 68, 78, 84, and 86). "[The first inter connector and the second inter connector connected] via etched portions of the isolator" (p. [0045], [0047], [0048], and Fig. 6, pts. 78, 84, and 92). "Wherein upper portions of the isolator are etched so that the first power line and the second power line are electrically connected with the first inter connector and the second inter connector, respectively" (p. [0045], [0047], [0048], and Fig. 6, pts. 68, 78, 84, 86, and 92). "The upper portions are positioned over the first power line and the second power line" (p. [0047], [0048], and Fig. 6, pts. 68, 86, and 92). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Matsubara and Tsuji with the teachings of Laflaquiere for the reasons provided above regarding claim 1.
The combination of Matsubara, Tsuji, and Laflaquiere does not explicitly disclose, "[The isolator] to prevent the first and second power lines from being exposed to external environment." Yu discloses, "[The isolator] to prevent the first and second power lines from being exposed to external environment" (p. [0029] and Fig. 8, pts. 204B and 206). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Matsubara, Tsuji, and Laflaquiere with the teachings of Yu for the reasons provided above regarding claim 1.
The combination of Matsubara, Tsuji, Laflaquiere, and Yu does not explicitly disclose, "One or more tunnel junctions formed between the respective multiple quantum well layers." Kim discloses, "One or more tunnel junctions formed between the respective multiple quantum well layers" (p. [0027] and Fig. 4, pts. 44 and 45). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Matsubara, Tsuji, Laflaquiere, and Yu with the teachings of Kim. In view of the teachings of Matsubara regarding a VCSEL having a multiple quantum well active layer, the alternate construction of the active region to include tunnel junctions between quantum well regions as taught by Kim would enhance the teachings of Matsubara, Tsuji, Laflaquiere, and Yu by allowing for higher efficiency operation.
Regarding claim 9, The combination of Matsubara, Tsuji, Laflaquiere, and Yu does not explicitly disclose, "Wherein the tunnel junction connects both adjacent multiple quantum well layers in series." Kim discloses, "Wherein the tunnel junction connects both adjacent multiple quantum well layers in series" (p. [0027] and Fig. 4, pts. 44 and 45). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Matsubara, Tsuji, Laflaquiere, and Yu with the teachings of Kim for the reasons provided above regarding claim 7.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Matsubara, in view of Tsuji, in view of Laflaquiere, in view of Yu, in view of Kim, and further in view of Burroughs.
Regarding claim 8, The combination of Matsubara, Tsuji, Laflaquiere, Yu, and Kim does not explicitly disclose, "Wherein the contact layer has a mesa structure only on one side of the micro VCSEL chip." Burroughs discloses, "Wherein the contact layer has a mesa structure only on one side of the micro VCSEL chip" (Fig. 2B, pts. 200 and 206). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Matsubara, Tsuji, Laflaquiere, Yu, and Kim with the teachings of Burroughs. In view of the teachings of Matsubara regarding a VCSEL having a current spreading layer, the alternate construction of the current spreading layer to extend only to one side of the mesa as taught by Burroughs would enhance the teachings of Matsubara, Tsuji, Laflaquiere, Yu, and Kim by allowing the footprint of the device to be reduced.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SEAN P HAGAN/Examiner, Art Unit 2828
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