DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS/IDSs) submitted on 11/13/2023 & 2/27/2025 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS/IDSs is/are being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 9, and 11-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by WIPO Patent Document No. WO2018004599A1 to Standfest et al.
Regarding claim 1, Standfest teaches an integrated circuit (IC) die comprising:
a hardware interface to couple the IC die to another IC die, wherein the IC die and the other IC die are to form, at least in part, a three-dimensional (3D) IC (figure 1A; ¶ [0032]: circuit 100 includes a plurality of TSV interconnects between layers 112-118);
a test unit to receive status information from a power management control (PMC) agent during an in-field operation of the 3D IC (figure 1A; ¶ [0032]: TSV controller 130 controls LCA logic block 120-126, generates TSV pass/fail mapping 140, and is triggered by TAP 150), the test unit further to:
detect, based on the status information, a first condition wherein a first partition of the IC die, and a second partition of the other IC die, are each in a respective idle state, wherein the 3D IC comprises a first lane between the first partition and the second partition (figure 1B; ¶¶ [0035]-[0038] & [0041]: TSV lanes 102-108, the LCA logic blocks operate in a low current mode to determine TSV fault/failure; compare logic 136 has a threshold indicating a TSV failure); and
detect a second condition wherein one or more communications via the first lane fail to satisfy a performance criteria (figure 1B; ¶¶ [0035]-[0038] & [0041]: TSV lanes 102-108, the LCA logic blocks operate in a low current mode to determine TSV fault/failure; compare logic 136 has a threshold indicating a TSV failure); and
mode circuitry coupled to the hardware interface and to the test unit; wherein, based on the second condition, and during the first condition, the test unit is to signal the mode circuitry to disable a first conductive path between the first lane and the first partition, and further to enable a second conductive path between a second lane of the 3D IC and the first partition (¶ [0039]: based on fail mapping 140, control 134 communicates with the LCAs 102-108 to replace a failed or failing TSV 102-106 with a redundant TSV 108).
Regarding claim 2, Standfest teaches the IC die of claim 1, wherein the test unit is a first test unit, and wherein:
multiple partitions of the 3D IC are each to correspond to a different respective one of multiple test units (¶ [0045]);
the multiple partitions are to comprise the first partition and the second partition (anytime there are multiple partitions, there must by definition be a first and second partition); and
for each test unit of the multiple test units:
the PMC agent is to be coupled to provide respective status information to the test unit (¶ [0036]); and
the test unit is to participate in a respective lane test based on the respective status information (¶ [0036]).
Regarding claim 3, Standfest teaches the IC die of claim 2, wherein the multiple partitions are each to operate in a first clock domain (¶ [0041]).
Regarding claim 4, Standfest teaches the IC die of claim 3, wherein the first condition is to be occur while one or more of the multiple partitions are each in a respective active state (¶ [0041]).
Regarding claim 5, Standfest teaches the IC die of claim 2, wherein:
the first partition comprises a first signal source circuit (504 bottom side);
the second partition is to comprise a first signal sink circuit (504 top side);
a third partition of the multiple partitions is to comprise a second signal source circuit of the other IC die (506 bottom side); and
a fourth partition of the multiple partitions comprises a second signal sink circuit of the IC die (506 top side).
Regarding claim 6, Standfest teaches the IC die of claim 1, wherein: the test unit is further to: receive test data from the PMC agent; and perform a communication of the test data from the IC die via the first lane; the other IC die is to generate a value based on the communication; and the test unit is to detect the second condition based on a mismatch between the value and a reference value (¶ [0038]: compare logic 136 determines whether a count value is higher or lower than a threshold indicating a TSV failure).
Regarding claim 7, Standfest teaches the IC die of claim 1, wherein: the test unit is further to receive performance information from a sensor which is coupled to the first lane; the test unit to detect the second condition comprises the test unit to identify, based on the performance information, a failure of a performance metric to satisfy a threshold condition; and the performance metric is to be based on one or more communications via the first lane (¶ [0049]: current sensor 410; determining based on the current 420 whether the circuit 100 is operating in a low current or high current mode by comparing with a threshold).
Regarding claim 9, Standfest teaches the IC die of claim 1, wherein interface circuitry, coupled between the PMC agent and the test unit, is to provide the status information via a bus which is compatible with a test bus standard (¶ [0079]-[0080] & element 1920).
Regarding claim 11, Standfest teaches a method comprising:
receiving, at a test unit of a first integrated circuit (IC) die, status information from a power management control (PMC) agent, wherein the first IC die and a second IC die are coupled to form, at least in part, a three-dimensional (3D) IC (figure 1A; ¶ [0032]: circuit 100 includes a plurality of TSV interconnects between layers 112-118), wherein the test unit receives the status information during an in-field operation of the 3D IC (figure 1A; ¶ [0032]: TSV controller 130 controls LCA logic block 120-126, generates TSV pass/fail mapping 140, and is triggered by TAP 150);
based on the status information, detecting a first condition wherein a first partition of the first IC die, and a second partition of the second IC die, are each in a respective idle state, wherein the 3D IC comprises a first lane between the first partition and the second partition (figure 1B; ¶¶ [0035]-[0038] & [0041]: TSV lanes 102-108, the LCA logic blocks operate in a low current mode to determine TSV fault/failure; compare logic 136 has a threshold indicating a TSV failure);
detecting a second condition wherein one or more communications via the first lane fail to satisfy a performance criteria (figure 1B; ¶¶ [0035]-[0038] & [0041]: TSV lanes 102-108, the LCA logic blocks operate in a low current mode to determine TSV fault/failure; compare logic 136 has a threshold indicating a TSV failure);
based on the second condition, and during the first condition:
disabling a first conductive path between the first lane and the first partition; and enabling a second conductive path between a second lane of the 3D IC and the first partition (¶ [0039]: based on fail mapping 140, control 134 communicates with the LCAs 102-108 to replace a failed or failing TSV 102-106 with a redundant TSV 108).
Regarding claim 12, Standfest teaches the method of claim 11, wherein the test unit is a first test unit, and wherein:
multiple partitions of the 3D IC each correspond to a different respective one of multiple test units (¶ [0045]);
the multiple partitions comprise the first partition and the second partition (anytime there are multiple partitions, there must by definition be a first and second partition); and
for each test unit of the multiple test units:
the PMC agent is coupled to provide respective status information to the test unit (¶ [0036]); and
the test unit is to participate in a respective lane test based on the respective status information (¶ [0036]).
Regarding claim 13, Standfest teaches the method of claim 12, wherein:
the first partition comprises a first signal source circuit (504 bottom side);
the second partition comprises a first signal sink circuit (504 top side);
a third partition of the multiple partitions comprises a second signal source circuit of the second IC die (506 bottom side); and
a fourth partition of the multiple partitions comprises a second signal sink circuit of the first IC die (506 top side).
Regarding claim 14, Standfest teaches the method of claim 11, further comprising:
receiving, at the test unit, test data from the PMC agent; and
performing a communication of the test data from the first IC die via the first lane; wherein the second IC die generates a value based on the communication, and wherein the second condition is detected based on a mismatch between the value and a reference value (¶ [0038]: compare logic 136 determines whether a count value is higher or lower than a threshold indicating a TSV failure).
Regarding claim 15, Standfest teaches the method of claim 11, further comprising:
receiving, at the test unit, performance information from a sensor which is coupled to the first lane; wherein detecting the second condition comprises identifying, based on the performance information, a failure of a performance metric to satisfy a threshold condition, wherein the performance metric is based on one or more communications via the first lane (¶ [0049]: current sensor 410; determining based on the current 420 whether the circuit 100 is operating in a low current or high current mode by comparing with a threshold).
Regarding claim 16, Standfest teaches a system comprising:
a first integrated circuit (IC) die and a second IC die coupled to each other to form, at least in part, a three-dimensional (3D) IC (figure 1A; ¶ [0032]: circuit 100 includes a plurality of TSV interconnects between layers 112-118), wherein the first IC die comprises:
a test unit to receive status information from a power management control (PMC) agent during an in-field operation of the 3D IC (figure 1A; ¶ [0032]: TSV controller 130 controls LCA logic block 120-126, generates TSV pass/fail mapping 140, and is triggered by TAP 150), the test unit further to:
detect, based on the status information, a first condition wherein a first partition of the IC die, and a second partition of the other IC die, are each in a respective idle state, wherein the 3D IC comprises a first lane between the first partition and the second partition (figure 1B; ¶¶ [0035]-[0038] & [0041]: TSV lanes 102-108, the LCA logic blocks operate in a low current mode to determine TSV fault/failure; compare logic 136 has a threshold indicating a TSV failure); and
detect a second condition wherein one or more communications via the first lane fail to satisfy a performance criteria (figure 1B; ¶¶ [0035]-[0038] & [0041]: TSV lanes 102-108, the LCA logic blocks operate in a low current mode to determine TSV fault/failure; compare logic 136 has a threshold indicating a TSV failure); and
mode circuitry coupled to the test unit; wherein, based on the second condition, and during the first condition, the test unit is to signal the mode circuitry to disable a first conductive path between the first lane and the first partition, and further to enable a second conductive path between a second lane of the 3D IC and the first partition (¶ [0039]: based on fail mapping 140, control 134 communicates with the LCAs 102-108 to replace a failed or failing TSV 102-106 with a redundant TSV 108); and
a memory interface to communicate a signal between the 3D IC and a memory (¶¶ [0079]-[0080]).
Regarding claim 17, Standfest teaches the system of claim 16, wherein the test unit is a first test unit, and wherein:
multiple partitions of the 3D IC are each to correspond to a different respective one of multiple test units (¶ [0045]);
the multiple partitions are to comprise the first partition and the second partition (anytime there are multiple partitions, there must by definition be a first and second partition); and
for each test unit of the multiple test units:
the PMC agent is to be coupled to provide respective status information to the test unit (¶ [0036]); and
the test unit is to participate in a respective lane test based on the respective status information (¶ [0036]).
Regarding claim 18, Standfest teaches the system of claim 17, wherein:
the first partition comprises a first signal source circuit (504 bottom side);
the second partition is to comprise a first signal sink circuit (504 top side);
a third partition of the multiple partitions is to comprise a second signal source circuit of the other IC die (506 bottom side); and
a fourth partition of the multiple partitions comprises a second signal sink circuit of the IC die (506 top side).
Regarding claim 19, Standfest teaches the system of claim 16, wherein: the test unit is further to: receive test data from the PMC agent; and perform a communication of the test data from the IC die via the first lane; the other IC die is to generate a value based on the communication; and the test unit is to detect the second condition based on a mismatch between the value and a reference value (¶ [0038]: compare logic 136 determines whether a count value is higher or lower than a threshold indicating a TSV failure).
Regarding claim 20, Standfest teaches the system of claim 16, wherein: the test unit is further to receive performance information from a sensor which is coupled to the first lane; the test unit to detect the second condition comprises the test unit to identify, based on the performance information, a failure of a performance metric to satisfy a threshold condition; and the performance metric is to be based on one or more communications via the first lane (¶ [0049]: current sensor 410; determining based on the current 420 whether the circuit 100 is operating in a low current or high current mode by comparing with a threshold).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Standfest in view of United States Patent App. Pub. No. 20160299190 to Shim.
Regarding claim 8, Standfest teaches the IC die of claim 7, but does not teach explicitly wherein the performance metric is a setup time metric.
However, Shim teaches wherein the performance metric is a setup time metric (¶¶ [0074]-[0076]).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the setup time metric of Shim with the die of Standfest in order to optimize pulse width of control signals, thereby striking the desired balance between power use and performance.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Standfest.
Regarding claim 10, Standfest teaches the IC die of claim 9, but does not teach explicitly wherein the test bus standard is identified in an Institute of Electrical and Electronics Engineers (IEEE) 1149.1 specification.
However, the use of the IEEE 1149.1 specification was ubiquitous in the art prior to the filing of the instant application (see, e.g., US20220413041A1 to Whetsel) and choosing to use a test bus complying with that standard would have been an obvious matter of design choice among one of a limited number of options available to one of ordinary skill in the art who desired the advantages of that particular standard (e.g., a non‑intrusive, minimal‑pin interface and board‑level testing without physical access).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
United States Patent App. Pub. No. 20230170243 to Or-Bach et al. discloses a 3d semiconductor device and structure with replacement gates.
United States Patent App. Pub. No. 20230104210 to Or-Bach et al. discloses a 3d semiconductor device and structure with redundancy.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Robert P Alejnikov whose telephone number is (571)270-5164. The examiner can normally be reached 10:00a-6:00p M-F.
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/ROBERT P ALEJNIKOV JR/Examiner, Art Unit 2857
/ARLEEN M VAZQUEZ/Supervisory Patent Examiner, Art Unit 2857
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