DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to claims filed on 8/12/2023. Claims 1-20 are pending.
Priority
Applicant’s claim for priority from application no. 63/397,457 filed 08/12/2022 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/18/25, 1/17/25, 1/16/25, 1/15/25, 1/8/25, 12/10/24, 10/30/24, 7/31/24, 4/21/24, 4/3/24, 2/16/24, 2/8/24, 1/25/24, 1/17/24, 12/29/23, 10/24/23, 9/28/23, 9/11/23, 9/6/23 are being considered by the examiner.
However, it is impractical for the examiner to review the references thoroughly with the number of references cited in this case. By initializing each of the cited references on the accompanying 1449 forms, the examiner is merely acknowledging the submission of the cited references and merely indicating that only a cursory review has been made of the cited references. 4. MPEP § 2004.13 states: It is desirable to avoid the submission of long lists of documents if it can be avoided. Eliminate clearly
irrelevant and marginally pertinent cumulative information. If a long list is submitted, highlight those documents which have been specifically brought to applicant's attention and/or are known to be of most significance. See Penn Yan Boats, Inc. V. Sea Lark Boats, Inc., 359 F. Supp. 948, 175 USPQ 260 (S.D. Fla. 1972), aft 'd, 479 F.2d 1338, 178 USPQ 577 (Sth Cir. 1973), cert. denied, 414 U.S. 874 (1974). But cf. Molins PLC V. Textron Inc., 48 F.3d 1172, 33 USPQ2d 1823 (Fed. Cir. 1995).
Further, it should be noted that an applicant's duty of disclosure of material and information is not satisfied by presenting a patent examiner with "a mountain of largely irrelevant material from which he is presumed to have been able, with his experience and with adequate time, to have found the critical [material]. It ignores the real world conditions under which examiners work." Rohm & Haas Co. V. Crystal Chemical CO., 722 F.2d 1556, 1573 [220 USPQ 289] (Fed. Cir. 1983), cert. Denied, 469 U.S. 851
(1984). Patent applicant has a duty not just to disclose pertinent prior art references but to make a disclosure in such a way as not to "bury" it within other disclosures of less relevant prior art; see Golden Valley Microwave Foods Inc. V. Weaver Popcorn Co. Inc., 24 USPQ2d 180i (N~D. Ind. 1992); Molins PLC V. Textron Inc., 26 USPQ2d 1889, at 1899 (D.Del 1992); Penn Yan Boats, Inc. V. Sea Lark Boats, Inc. et al., 175 USPQ 260, at 272 (S.D. FI. 1972).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 6-12, 14, 15, and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sankaran et al. (U.S. PG Pub 20190347125; hereinafter referred to as Sankaran), in view of Huang et al. (U.S. PG Pub 20190228169; hereinafter referred to as Huang).
As per claim 1, Sankaran teaches:
a work queue circuit to store one or more descriptors (e.g. Sankaran: [0160] discloses shared work queues store descriptors submitted by multiple applications);
an arbiter circuit to dispatch a descriptor from the work queue (e.g. Sankaran: [0160] discloses a hardware interface/arbiter dispatches descriptors from the work queues),
wherein the descriptor comprises an operation field capable of specifying an inter-domain operation to be performed (e.g. Sankaran: [0503] discloses a descriptor 1300 which includes an operation field 3801 to specify the operation to be performed),
a submitter Process Address Space Identifier (PASID) field capable of specifying a submitter PASID of a submitter process to be executed on a processor (e.g. Sankaran: [0503] discloses one implementation of a descriptor 1300 which includes… a process address space identifier (PASID) field 3803.),
and a handle for a destination PASID associated with an address space of another process (e.g. Sankaran: [0503] discloses one implementation of a descriptor 1300 which includes… one or more operation-specific fields 3809. Please note descriptor 1300 can accommodate various types of operations and the operation-specific fields 3809 would encompass the fields needed for an inter-domain operation which corresponds to Applicant's a handle for a destination PASID associated with an address space of another process.);
and process the descriptor based at least in part on the inter-domain operation specified by the operation field (e.g. Sankaran: [0479] discloses Descriptors specify the type of operation for DSA to perform. [0482] discloses The device dispatches descriptors from the work queues 3511-3512 and submits them to the engines for further processing. Please note if the engines are going to process the descriptors, it necessarily follows some of the processing is going to deal with the operation in the descriptor which corresponds with Applicant’s descriptor processing based in part on the operation field.).
But Sankaran does not teach an engine circuit to: verify, based at least in part on the submitter PASID and the destination PASID handle, whether the submitter process is permitted to access the address space of the other process.
However, Huang does teach an engine circuit to: verify, based at least in part on the submitter (e.g. Huang: [0008] discloses The permission processing circuit searches a permission lookup table according to a device identifier corresponding to the function circuit and the range identifier to determine an operation permission of the function circuit for operating the physical address of the memory. Please note the function circuit with a device identifier and the permission processing circuit corresponds to Applicant's submitter process and engine circuit respectively.).
Sankaran and Huang are in the same field of endeavor in terms of memory management and therefore it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Sankaran with the teachings of Huang for an engine circuit to: verify, based at least in part on the submitter PASID and the destination PASID handle, whether the submitter process is permitted to access the address space of the other process. Sankaran already teaches the submitter PASID and destination PASID. By then combining it with Huang’s idea of using a circuit to verify if a requesting entity has permission to access a specific memory space, this increases security within the system. Because according to Huang [0003], “Under the consideration of information security, a system needs to control operation permissions of function circuits.”
As per claim 2, Sankaran-Huang teaches claim 1 as applied above. Sankaran further teaches wherein the inter-domain operation to be performed is at least one of: a copy operation, a fill operation, a compare operation, a compare pattern operation, and a flush operation (e.g. Sankaran: [0630] discloses The Memory Move operation 4308 copies memory from the Source Address 4302 to the Destination Address 4303. [0634] discloses The Memory Fill operation 4408 fills memory at the Destination Address 4406 with the value in the pattern field 4405. [0636] discloses The Compare operation 4508 compares memory at Source1 Address 4504 with memory at Source2 Address 4505. [0639] discloses The Compare Immediate operation 4608 compares memory at Source Address 4601 with the value in the pattern field 4602. [0675] discloses The Cache Flush operation 5705 flushes the processor caches at the Destination Address.).
As per claim 6, Sankaran-Huang teaches claim 1 as applied above. Sankaran further teaches wherein a hardware accelerator comprises the work queue, the arbiter, and the engine (e.g. Sankaran: [0160] discloses a work queue (either shared or dedicated) receives descriptors. [0160] further discloses A hardware interface/arbiter dispatches descriptors from the work queues to the accelerator processing engines.).
As per claim 7, Sankaran-Huang teaches claim 6 as applied above. Sankaran further teaches wherein the hardware accelerator is to perform data movement or data transformation for data to be transmitted between the processor and a storage device (e.g. Sankaran: [0630] discloses an exemplary memory move descriptor 4300 and memory move completion record 4301. The Memory Move operation 4308 copies memory from the Source Address 4302 to the Destination Address 4303. Please note copying memory from a source address to a destination address corresponds to Applicant's data movement between a processor and storage device. This is because the source and destination addresses could both be either a processor or storage device.).
As per claim 8, Sankaran-Huang teaches claim 6 as applied above. Sankaran further teaches wherein a System On Chip (SOC) device comprises the hardware accelerator and the processor (e.g. Sankaran: [0148] discloses Accelerators are typically hardware devices (circuits) that perform functions more efficiently than software running on a general purpose processor. [0149] discloses The power budget of a given system (e.g., system-on-a-chip (“SOC”), processor stock unit, rack, etc.) can be consumed by processing elements on only a fraction of the available silicon area. This makes it advantageous to build a variety of specialized hardware blocks that reduce energy consumption for specific operations. Please note the specialized hardware blocks built on a system-on-a-chip correspond to Applicant’s system on chip comprising a hardware accelerator. This is because a specialized hardware block would include something like a hardware accelerator. Please note the text grouped the SOC and processor stock unit together under a system that shares a power budget which corresponds to Applicant’s system on chip comprising a processor. But also, in general engineering a SOC by definition integrates a processor.).
As per claim 9, Sankaran-Huang teaches claim 1 as applied above. Sankaran further teaches wherein the work queue is to be configured as a Shared Work Queue (SWQ) or a Dedicated Work Queue (DWQ), wherein the SWQ is to be shared by multiple software applications, whereas the DWQ is to be assigned to a single software application (e.g. Sankaran: [0160] discloses a work queue (either shared or dedicated) receives descriptors which define the scope of work to be done by a device. Dedicated work queues store descriptors for a single application while shared work queues store descriptors submitted by multiple applications).
As per claim 10, Sankaran-Huang teaches claim 1 as applied above. Sankaran further teaches wherein the processor comprises one or more processor cores to execute the submitter process (e.g. Sankaran: [0473] discloses a data streaming accelerator (DSA)… uses the I/O fabric interface 3501 for receiving downstream work requests from clients (such as processor cores. Please note the processor cores sending the work requests to the DSA corresponds to Applicant’s one or more processor cores to execute the submitter process. This is because the work requests are descriptors that are obtained once the processors run the submitter process so that the work requests (descriptors) can be sent to the DSA.).
As per claim 11, Sankaran teaches:
storing one or more descriptors in a work queue (e.g. Sankaran: [0160] discloses shared work queues store descriptors submitted by multiple applications);
dispatching, at an arbiter, a descriptor from the work queue (e.g. Sankaran: [0160] discloses a hardware interface/arbiter dispatches descriptors from the work queues),
wherein the descriptor comprises an operation field capable of specifying an inter-domain operation to be performed (e.g. Sankaran: [0503] discloses a descriptor 1300 which includes an operation field 3801 to specify the operation to be performed),
a submitter Process Address Space Identifier (PASID) field capable of specifying a submitter PASID of a submitter process to be executed on a processor (e.g. Sankaran: [0503] discloses one implementation of a descriptor 1300 which includes… a process address space identifier (PASID) field 3803.),
and a handle for a destination PASID associated with an address space of another process (e.g. Sankaran: [0503] discloses one implementation of a descriptor 1300 which includes… one or more operation-specific fields 3809. Please note descriptor 1300 can accommodate various types of operations and the operation-specific fields 3809 would encompass the fields needed for an inter-domain operation which corresponds to Applicant's a handle for a destination PASID associated with an address space of another process.);
and processing, at the engine, the descriptor based at least in part on the inter- domain operation specified by the operation field (e.g. Sankaran: [0479] discloses Descriptors specify the type of operation for DSA to perform. [0482] discloses The device dispatches descriptors from the work queues 3511-3512 and submits them to the engines for further processing. Please note if the engines are going to process the descriptors, it necessarily follows some of the processing is going to deal with the operation in the descriptor which corresponds with Applicant’s descriptor processing based in part on the operation field.).
But Sankaran does not teach verifying, at an engine, based at least in part on the submitter PASID and the destination PASID handle, whether the submitter process is permitted to access the address space of another process.
However, Huang does teach verifying, at an engine, based at least in part on the submitter (e.g. Huang: [0008] discloses The permission processing circuit searches a permission lookup table according to a device identifier corresponding to the function circuit and the range identifier to determine an operation permission of the function circuit for operating the physical address of the memory. Please note the function circuit with a device identifier and the permission processing circuit corresponds to Applicant's submitter process and engine circuit respectively.).
Sankaran and Huang are in the same field of endeavor in terms of memory management and therefore it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Sankaran with the teachings of Huang for verifying, at an engine, based at least in part on the submitter PASID and the destination PASID handle, whether the submitter process is permitted to access the address space of another process. Sankaran already teaches the submitter PASID and destination PASID. By then combining it with Huang’s idea of using a circuit to verify if a requesting entity has permission to access a specific memory space, this increases security within the system. Because according to Huang [0003], “Under the consideration of information security, a system needs to control operation permissions of function circuits.”
As per claim 12, Sankaran-Huang teaches claim 11 as applied above. Sankaran further teaches performing the inter-domain operation by executing at least one of: a copy operation, a fill operation, a compare operation,a compare pattern operation, and a flush operation (e.g. Sankaran: [0630] discloses The Memory Move operation 4308 copies memory from the Source Address 4302 to the Destination Address 4303. [0634] discloses The Memory Fill operation 4408 fills memory at the Destination Address 4406 with the value in the pattern field 4405. [0636] discloses The Compare operation 4508 compares memory at Source1 Address 4504 with memory at Source2 Address 4505. [0639] discloses The Compare Immediate operation 4608 compares memory at Source Address 4601 with the value in the pattern field 4602. [0675] discloses The Cache Flush operation 5705 flushes the processor caches at the Destination Address.).
As per claim 14, Sankaran teaches:
a processor to execute one or more processes (e.g. Sankaran: [Fig. 30] discloses processor cores 3003);
an Input/Output (IO) fabric to transfer data between an accelerator device and a storage unit (e.g. Sankaran: [0473] discloses a data streaming accelerator (DSA) device comprising multiple work queues 3511-3512 which receive descriptors submitted over an I/O fabric interface 3501 (e.g., such as the multi-protocol link 2800 described above). [0372] discloses this implementation includes an accelerator 2801 with an accelerator memory 2850 coupled over a multi-protocol link 2800 to a host processor 2802 with a host memory 2860.);
a work queue circuit to store one or more descriptors (e.g. Sankaran: [0160] discloses shared work queues store descriptors submitted by multiple applications);
an arbiter circuit to dispatch a descriptor from the work queue (e.g. Sankaran: [0160] discloses a hardware interface/arbiter dispatches descriptors from the work queues),
wherein the descriptor comprises an operation field capable of specifying an inter-domain operation to be performed (e.g. Sankaran: [0503] discloses a descriptor 1300 which includes an operation field 3801 to specify the operation to be performed),
a submitter Process Address Space Identifier (PASID) field capable of specifying a submitter PASID of a submitter process to be executed on the processor (e.g. Sankaran: [0503] discloses one implementation of a descriptor 1300 which includes… a process address space identifier (PASID) field 3803.),
and a handle for a destination PASID associated with an address space of another process (e.g. Sankaran: [0503] discloses one implementation of a descriptor 1300 which includes… one or more operation-specific fields 3809. Please note descriptor 1300 can accommodate various types of operations and the operation-specific fields 3809 would encompass the fields needed for an inter-domain operation which corresponds to Applicant's a handle for a destination PASID associated with an address space of another process.);
and process the descriptor based at least in part on the inter-domain operation specified by the operation field (e.g. Sankaran: [0479] discloses Descriptors specify the type of operation for DSA to perform. [0482] discloses The device dispatches descriptors from the work queues 3511-3512 and submits them to the engines for further processing. Please note if the engines are going to process the descriptors, it necessarily follows some of the processing is going to deal with the operation in the descriptor which corresponds with Applicant’s descriptor processing based in part on the operation field.).
But Sankaran does not teach an engine circuit to: verify, based at least in part on the submitter PASID and the destination PASID handle, whether the submitter process is permitted to access the address space of the other process.
However, Huang does teach an engine circuit to: verify, based at least in part on the submitter (e.g. Huang: [0008] discloses The permission processing circuit searches a permission lookup table according to a device identifier corresponding to the function circuit and the range identifier to determine an operation permission of the function circuit for operating the physical address of the memory. Please note the function circuit with a device identifier and the permission processing circuit corresponds to Applicant's submitter process and engine circuit respectively.).
Sankaran and Huang are in the same field of endeavor in terms of memory management and therefore it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Sankaran with the teachings of Huang for an engine circuit to: verify, based at least in part on the submitter PASID and the destination PASID handle, whether the submitter process is permitted to access the address space of the other process. Sankaran already teaches the submitter PASID and destination PASID. By then combining it with Huang’s idea of using a circuit to verify if a requesting entity has permission to access a specific memory space, this increases security within the system. Because according to Huang [0003], “Under the consideration of information security, a system needs to control operation permissions of function circuits.”
As per claim 15, Sankaran-Huang teaches claim 14 as applied above. Sankaran further teaches wherein the inter-domain operation to be performed is at least one of: a copy operation, a fill operation, a compare operation, a compare pattern operation, and a flush operation (e.g. Sankaran: [0630] discloses The Memory Move operation 4308 copies memory from the Source Address 4302 to the Destination Address 4303. [0634] discloses The Memory Fill operation 4408 fills memory at the Destination Address 4406 with the value in the pattern field 4405. [0636] discloses The Compare operation 4508 compares memory at Source1 Address 4504 with memory at Source2 Address 4505. [0639] discloses The Compare Immediate operation 4608 compares memory at Source Address 4601 with the value in the pattern field 4602. [0675] discloses The Cache Flush operation 5705 flushes the processor caches at the Destination Address.).
As per claim 18, Sankaran-Huang teaches claim 14 as applied above. Sankaran further teaches wherein the hardware accelerator is to perform data movement or data transformation for data to be transmitted between the processor and a storage device (e.g. Sankaran: [0630] discloses an exemplary memory move descriptor 4300 and memory move completion record 4301. The Memory Move operation 4308 copies memory from the Source Address 4302 to the Destination Address 4303. Please note copying memory from a source address to a destination address corresponds to Applicant's data movement between a processor and storage device. This is because the source and destination addresses could both be either a processor or storage device.).
As per claim 19, Sankaran-Huang teaches claim 14 as applied above. Sankaran further teaches wherein a System On Chip (SOC) device comprises the hardware accelerator and the processor (e.g. Sankaran: [0148] discloses Accelerators are typically hardware devices (circuits) that perform functions more efficiently than software running on a general purpose processor. [0149] discloses The power budget of a given system (e.g., system-on-a-chip (“SOC”), processor stock unit, rack, etc.) can be consumed by processing elements on only a fraction of the available silicon area. This makes it advantageous to build a variety of specialized hardware blocks that reduce energy consumption for specific operations. Please note the specialized hardware blocks built on a system-on-a-chip correspond to Applicant’s system on chip comprising a hardware accelerator. This is because a specialized hardware block would include something like a hardware accelerator. Please note the text grouped the SOC and processor stock unit together under a system that shares a power budget which corresponds to Applicant’s system on chip comprising a processor. But also, in general engineering a SOC by definition integrates a processor.).
As per claim 20, Sankaran-Huang teaches claim 14 as applied above. Sankaran further teaches wherein the work queue is to be configured as a Shared Work Queue (SWQ) or a Dedicated Work Queue (DWQ), wherein the SWQ is to be shared by multiple software applications, whereas the DWQ is to be assigned to a single software application (e.g. Sankaran: [0160] discloses a work queue (either shared or dedicated) receives descriptors which define the scope of work to be done by a device. Dedicated work queues store descriptors for a single application while shared work queues store descriptors submitted by multiple applications).
Claim(s) 3, 4, 13, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sankaran-Huang, in view of Asanovic et al. (U.S. Patent 7287140; hereinafter referred to as Asanovic).
As per claim 3, Sankaran-Huang teaches claim 1 as applied above. But Sankaran-Huang does not teach further comprising a cache to store a bit map associated with one or more submitter processes that are allowed to submit the inter-domain operation.
However, Asanovic does teach further comprising a cache to store a bit map associated with one or more submitter processes that are allowed to submit the inter-domain operation (e.g. Asanovic: [0028] discloses The memory 30 includes a permissions table 40 stored in a privileged space of the memory 30. The permissions table 40 holds metadata values arranged as "protection domains." [0028] further discloses Metadata values stored in the permissions table 40 can each include, but are not limited to, a respective permission value. Exemplary permission values are shown in Table 1 below. Permission values can include, but are not limited to, a read-only value, a write-only value, a read-write value, an execute-read value, an execute-write value, an execute-read-write value, an execute-only value, and a no-permission value. Please note the permissions table holds the values that tell whether software have the permission to perform some operation which corresponds to Applicant’s bit map associated with submitter processes that are allowed to submit operations.
[0114] discloses The protection lookaside buffer (PLB) 18 (FIG. 1) caches entries form the permissions table 40 (FIG. 1). Please note the protection lookaside buffer caching entries from the permissions table which corresponds to Applicant’s caching the bit map.).
Sankaran-Huang and Asanovic are in the same field of endeavor in terms of memory management and therefore it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Sankaran-Huang with the teachings of Asanovic for further comprising a cache to store a bit map associated with one or more submitter processes that are allowed to submit the inter-domain operation. This improves system speed and efficiency. Instead of needing to traverse complex tables, structures, and lists to determine if a process has permissions, the hardware can evaluate it quickly by looking at a cached bit map. Forgoing the costly traversal saves both time and resources.
As per claim 4, Sankaran-Huang-Asanovic teaches claim 3 as applied above. Sankaran-Huang-Asanovic further teaches
wherein a hardware accelerator comprises the work queue, the arbiter, the engine (e.g. Sankaran: [0160] discloses a work queue (either shared or dedicated) receives descriptors. [0160] further discloses A hardware interface/arbiter dispatches descriptors from the work queues to the accelerator processing engines.),
and the cache (e.g. Asanovic: [0114] discloses The protection lookaside buffer (PLB) 18 (FIG. 1) caches entries form the permissions table 40 (FIG. 1).).
As per claim 13, Sankaran-Huang teaches claim 11 as applied above. But Sankaran-Huang does not teach further comprising storing a bit map, associated with one or more submitter processes that are allowed to submit the inter-domain operation,in a cache.
However, Asanovic does teach further comprising storing a bit map, associated with one or more submitter processes that are allowed to submit the inter-domain operation,in a cache (e.g. Asanovic: [0028] discloses The memory 30 includes a permissions table 40 stored in a privileged space of the memory 30. The permissions table 40 holds metadata values arranged as "protection domains." [0028] further discloses Metadata values stored in the permissions table 40 can each include, but are not limited to, a respective permission value. Exemplary permission values are shown in Table 1 below. Permission values can include, but are not limited to, a read-only value, a write-only value, a read-write value, an execute-read value, an execute-write value, an execute-read-write value, an execute-only value, and a no-permission value. Please note the permissions table holds the values that tell whether software have the permission to perform some operation which corresponds to Applicant’s bit map associated with submitter processes that are allowed to submit operations.
[0114] discloses The protection lookaside buffer (PLB) 18 (FIG. 1) caches entries form the permissions table 40 (FIG. 1). Please note the protection lookaside buffer caching entries from the permissions table which corresponds to Applicant’s caching the bit map.).
Sankaran-Huang and Asanovic are in the same field of endeavor in terms of memory management and therefore it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Sankaran-Huang with the teachings of Asanovic for further comprising storing a bit map, associated with one or more submitter processes that are allowed to submit the inter-domain operation,in a cache. This improves system speed and efficiency. Instead of needing to traverse complex tables, structures, and lists to determine if a process has permissions, the hardware can evaluate it quickly by looking at a cached bit map. Forgoing the costly traversal saves both time and resources.
As per claim 16, Sankaran-Huang teaches claim 14 as applied above. But Sankaran-Huang does not teach wherein the accelerator device comprises a cache to store a bit map associated with one or more submitter processes that are allowed to submit the inter-domain operation.
However, Asanovic does teach (e.g. Asanovic: [0028] discloses The memory 30 includes a permissions table 40 stored in a privileged space of the memory 30. The permissions table 40 holds metadata values arranged as "protection domains." [0028] further discloses Metadata values stored in the permissions table 40 can each include, but are not limited to, a respective permission value. Exemplary permission values are shown in Table 1 below. Permission values can include, but are not limited to, a read-only value, a write-only value, a read-write value, an execute-read value, an execute-write value, an execute-read-write value, an execute-only value, and a no-permission value. Please note the permissions table holds the values that tell whether software have the permission to perform some operation which corresponds to Applicant’s bit map associated with submitter processes that are allowed to submit operations.
[0114] discloses The protection lookaside buffer (PLB) 18 (FIG. 1) caches entries form the permissions table 40 (FIG. 1). Please note the protection lookaside buffer caching entries from the permissions table which corresponds to Applicant’s caching the bit map.).
Sankaran-Huang and Asanovic are in the same field of endeavor in terms of memory management and therefore it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Sankaran-Huang with the teachings of Asanovic for . This improves system speed and efficiency. Instead of needing to traverse complex tables, structures, and lists to determine if a process has permissions, the hardware can evaluate it quickly by looking at a cached bit map. Forgoing the costly traversal saves both time and resources.
Claim(s) 5 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sankaran-Huang-Asanovic, in view of Balaji et al. (CN 101027652 A; published August 29, 2007; English Translation Provided by IP.com; hereinafter referred to as Balaji).
As per claim 5, Sankaran-Huang-Asanovic teaches claim 3, as applied above. But Sankaran-Huang-Asanovic does not teach wherein an invalidation command is to be issued in response to a determination that the bit map has been modified.
However, Balaji does teach wherein an invalidation command is to be issued in response to a determination that the bit map has been modified (e.g. Balaji: [Page 17 Paragraph 5] discloses Expectation software makes the filtered bitmap cache invalidation clearly when non-heavy allocation domain being added or remove the page. Please note adding a page modifies the memory which in turn affects the bitmap. This causes the bitmap cache to be invalidated which corresponds to Applicant's invalidation command in response to bit map modification.).
Sankaran-Huang-Asanovic and Balaji are in the same field of endeavor in terms of memory management and therefore it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Sankaran-Huang-Asanovic with the teachings of Balaji for wherein an invalidation command is to be issued in response to a determination that the bit map has been modified. This causes the system to be less likely to run into an error by ensuring the hardware does not use stale data after the software updates or modifies memory.
As per claim 17, Sankaran-Huang-Asanovic teaches claim 16, as applied above. But Sankaran-Huang-Asanovic does not teach wherein an invalidation command is to be issued in response to a determination that the bit map has been modified.
However, Balaji does teach wherein an invalidation command is to be issued in response to a determination that the bit map has been modified (e.g. Balaji: [Page 17 Paragraph 5] discloses Expectation software makes the filtered bitmap cache invalidation clearly when non-heavy allocation domain being added or remove the page. Please note adding a page modifies the memory which in turn affects the bitmap. This causes the bitmap cache to be invalidated which corresponds to Applicant's invalidation command in response to bit map modification.).
Sankaran-Huang-Asanovic and Balaji are in the same field of endeavor in terms of memory management and therefore it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Sankaran-Huang-Asanovic with the teachings of Balaji for wherein an invalidation command is to be issued in response to a determination that the bit map has been modified. This causes the system to be less likely to run into an error by ensuring the hardware does not use stale data after the software updates or modifies memory.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US12554869 talks about checking if some software has permission to work with some data input
CN 113924557 A talks about an accelerator device performing on some data block
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL N TRUONG whose telephone number is (571)270-0856. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, April Blair can be reached at (571) 270-1014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DANIEL NHU TRUONG/Examiner, Art Unit 2196
/APRIL Y BLAIR/Supervisory Patent Examiner, Art Unit 2196
