DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 10-11, and 14-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tanaka et al. (hereinafter “Tanaka”, US Pat No. 2020/0212846).
As per claim 1, Tanaka disclosed a power amplification system (see fig. 1), the power amplification system comprising a cascode power amplifier PA (see fig. 1, transistor 111) configured to receive and amplify a radio-frequency RF signal, the cascode PA including a shared common cascode input stage (see fig.1, RF in); and a plurality of cascode output stages (see fig. 1, transistors 112, 113, and 114) parallelly connected to the shared common cascode input stage, and wherein each cascode output stage associated with a frequency band (see at least fig. 4, Band 1, Band 2).
As per claims 2 and 15, Tanaka disclosed the plurality of cascode output stages include a first cascode output stage (see fig. 1, transistor 112, and RF out1) and a second cascode output stage (see fig. 1, transistor 113, and RF out2), the first cascode output stage associated with a first frequency band (see at least fig. 4, Band 1), and a second cascode output stage associated with a second frequency band (see at least fig. 4, Band 2).
As per claims 3 and 16, Tanaka disclosed the first cascode output stage receives an amount of voltage that activates the first cascode output stage to provide a first amplification path for the RF signal while the second cascode output stage does not receive the amount of voltage and does not provide a second amplification path (see 0040-0044, the transistors 112, 113, and 114 are switched, by the presence or absence of bias currents or voltages from the respective bias circuits 212, 213, and 214, between an on state in which a signal is amplified and an off state in which a signal is not amplified).
As per claims 4 and 17, Tanaka disclosed the first cascode output stage stops receiving the amount of voltage and stops providing the first amplification path for the RF signal while the second cascode output stage receives the amount of voltage to provide the second amplification path for the RF signal (see 0040-0044, the transistors 112, 113, and 114 are switched, by the presence or absence of bias currents or voltages from the respective bias circuits 212, 213, and 214, between an on state in which a signal is amplified and an off state in which a signal is not amplified).
As per claims 5 and 18, Tanaka disclosed provision of the first amplification path and the second amplification path alternates in a non-overlapping manner (see 0044).
As per claim 6, Tanaka disclosed the cascode input stage includes a first bipolar junction transistor (BJT), the first cascode output stage includes a second BJT, the second cascode output stage includes a third BJT (see fig. 1, all transistors 111-1114 are of BJT type), and a voltage greater than a forward-biasing voltage is applied to the second BJT while not applied to the third BJT (see 0044, the transistors 112, 113, and 114 are switched, by the presence or absence of bias currents or voltages from the respective bias circuits 212, 213, and 214, between an on state in which a signal is amplified and an off state in which a signal is not amplified. The characteristics of the activation of the amplifier is when the applied bias voltage meet or exceed the threshold (presence) the amplifier is active and when the bias voltage does not meet the threshold (absence) the amplifier remain idle).
As per claim 7, Tanaka the cascode input stage includes a BJT, the first cascode output stage includes a first field-effect-transistor (FET), the second cascode output stage includes a second FET (see 0028), and a voltage greater than a threshold voltage is applied to the first FET while not applied to the second FET (see rejection above in claim 6).
As per claim 10, Tanaka disclosed the plurality of cascode output stages have impedances of approximately 50 Ohms (see 0089, 0092-0095, 0102, and at least 0117).
As per claim 11, Tanaka disclosed a transmit Tx filter (see at least fig. 4, filter Band 1 Tx) coupled to the first cascode output stage and configured to condition a signal output by the first cascode output stage, the Tx filter configured to operate in the first frequency band.
As per claim 14, as rejected above in claim 1, Tanaka further disclosed a wireless device (see 0003, mobile phone) comprising a transceiver (see at least fig. 4) configured to generate a radio-frequency (RF) signal; a front-end module FEM (see at least fig. 4, 20) in communication with the transceiver, the FEM including a packaging substrate configured to receive a plurality of components, the FEM further including a power amplification system (see at least fig. 4, 10) implemented on the packaging substrate, the power amplification system including a cascode power amplifier (PA), the cascode PA including a shared common cascode input stage and a shared common cascode input stage and a plurality of cascode output stages parallelly connected to the shared common cascode input stage, each cascode output stage associated with a frequency band, the cascode PA configured to receive and amplify a radio-frequency (RF) signal (see rejection above in claim 1); and an antenna (see at least fig. 4, antenna 62) in communication with the FEM, the antenna configured to transmit the amplified RF signal.
As per claim 19, Tanaka disclosed the Tx filter is coupled to the first cascode output stage by an amplification path that is free of a band select switch (see fig. 4, no band select switch).
As per claim 20, as rejected above in claim 1, Tanaka further disclosed a method for processing a radio-frequency (RF) signal, the method comprising: providing a cascode power amplifier (PA) including a shared cascode input stage and a first cascode output stage and a second cascode output stage parallelly connected to the shared cascode input stage, the first cascode output stage associated with a first frequency band and the second cascode output stage associated with a second frequency band (see rejection above in claim 2); applying an amount of voltage that activates the first cascode output stage to provide a first amplification path while not applying the amount of voltage to the second output stage to block a second amplification path (see 0040-0044, the transistors 112, 113, and 114 are switched, by the presence or absence of bias currents or voltages from the respective bias circuits 212, 213, and 214, between an on state in which a signal is amplified and an off state in which a signal is not amplified); amplifying the RF signal with the cascode PA with the shared cascode input stage and the first cascode output stage through the first amplification path (see fig. 1, wherein the RF in will be amplified by the cascode amplifier 111 and routed to the first path and amplified by the first cascode output stage, see amplifier 112)); routing the amplified RF signal to a downstream filter associated with the first frequency band (see at least fig. 4, filter Band1 TX).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka in view of Xu et al. (hereinafter “Xu”, US Pat No. 2016/0036388)
As per claim 8, Tanaka disclosed a voltage supply system configured to provide a voltage (see fig. 1, Vcc3) to the plurality of cascode output stages but does not disclosed wherein the voltage supply system includes a boost DC/DC converter configured to generate the voltage (in the range of greater than or equal to 11V) based on a battery voltage. However, Xu disclose such voltage supply system includes a boost DC/DC converter includes a boost DC/DC converter (see Fig. 1, 120). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention for Tanaka to utilize the teaching of Xu in order to provide efficiently for average powers when biased at the system supply voltage.
The improved communication of Tanaka and Xu disclosed such that the voltage supply system configured to generate the voltage in the range of 3.0V to 6.3V but not in the range greater than or equal to 11. However, such a voltage range, as claimed, can be implement is based upon design or system requirements.
As per claim 9, The improved communication of Tanaka and Xu disclosed the voltage is provided to collectors of the plurality of cascode output stages (see Tanaka, fig. 1, Vcc3 applied the collector of amplifiers 212, 213, & 214).
Claim(s) 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka and in view of Pourghorban Saghati et al. (hereinafter “Pourghorban Saghati”, US Pat No. 11,831,061).
As per claim 12, Tanaka does not disclosed that the Tx filter is coupled to the first cascode output stage by an amplification path that is free of an impedance transformation circuit. However, such teaching of a power amplification module does not utilize a commonly known matching impedance are well-known in the art, as taught by Pourghorban Saghati (see 0049 and 0082). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention for Tanaka to utilize the reaching of Pourghorban Saghati in order to improve performance of the modules across a wider range of frequency bands while save cost and space.
As per claim 13, see rejection above in claim 19.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Pablo Tran whose telephone number is (571)272-7898. The examiner normal hours are 9:30 -5:00 (Monday-Friday). If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jinsong Hu, can be reached at (571)272-3965. The fax phone number for the organization where this application or proceeding is assigned is (571)273-8300.
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April 29, 2026
/PABLO N TRAN/Primary Examiner, Art Unit 2643
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