Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has been amended to overcome the objection to the specification. The objection to the specification is withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claim 1 sets forth “and out of at least three different possible settings, determining which data states are to be verified”. Although the specification appears to provide support for the limitation “determining an output of the analog bitscan operation, the output being one of at least three options” as set forth in the claim, there is insufficient support for “and out of at least three different possible settings, determining which data states are to be verified”. In particular, one of ordinary skill in the art would require clarification as to what constitutes a “setting” as set forth by “at least three different possible settings” in the claim. If “setting” is intended to refer to possible data states, this is not described in the specification as to enable one skilled in the art to make and/or use the invention. Appropriate clarification is required.
Claims 2-4 are rejected as dependent upon claim 1.
Claim 5 sets forth “the output of the analog bitscan affecting the which of at least three different possible settings of the smart verify programming voltage is chosen.”
Although the specification appears to provide support for the limitation “determining an output of the analog bitscan operation, the output being one of at least three options” as set forth in the claim, there is insufficient support for “the output of the analog bitscan affecting the which of at least three different possible settings of the smart verify programming voltage is chosen”. In particular, one of ordinary skill in the art would require clarification as to what constitutes a “setting” as set forth by “at least three different possible settings” in the claim. If “setting” is intended to refer to possible data states, this is not described in the specification as to enable one skilled in the art to make and/or use the invention. Appropriate clarification is required.
Claims 6-10 are rejected as dependent upon claim 5.
Claim 11 sets forth “or a smart verify parameter, there being at least three different possible settings for the program-verify termination parameter or for the smart verify parameter to be selected from based on which of the at least three options is the output of the analog bitscan operation”. One of ordinary skill in the art would not understand how to make and/or use an invention with such limitations, and further support is required in the written description to enable such a claim. Appropriate correction is required.
Claims 12-20 are rejected as dependent upon claim 11.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 sets forth “the output of the analog bitscan affecting the which of at least three different possible settings of the smart verify programming voltage is chosen.” This language is unclear. Appropriate correction is required.
Claims 6-10 are rejected as dependent upon claim 5.
Claim 11 sets forth “or a smart verify parameter, there being at least three different possible settings for the program-verify termination parameter or for the smart verify parameter to be selected from based on which of the at least three options is the output of the analog bitscan operation.” This language is unclear. Appropriate correction is required.
Claims 12-20 are rejected as dependent upon claim 11.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 5-6, 11-13, and 16-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US20220336019 (Prakash, et al.) hereinafter Prakash.
Resolution of indefiniteness issues is required. In the interest of compact prosecution, the art-based rejections are provided given broad interpretation.
Regarding claim 1, Prakash teaches a method of performing a programming operation in a memory device, (Prakash, [0001]: “relates to the operation of memory
devices”; Prakash, FIG. 1A-6D) comprising the steps of: preparing a memory block that includes a plurality of memory cells that are arranged in a plurality of word lines, (Prakash, [0002]: “In an EEPROM or flash NAND array architecture, memory cells may be arranged in a matrix of rows and columns such that gates of each memory cell are coupled by rows to word lines. The memory cells may be arranged together in strings such that memory cells in a given string are coupled together in series, from source to drain, between a common source line and a common bit line.”) the plurality of word lines including a selected word line; (Prakash, [0005]: “The method includes the step of programming memory cells of a selected word line to a first programmed data state”) programming at least some of the plurality of memory cells of the selected word line to at least three bits of data per memory cell (Prakash, FIG. 10; [0057]: “As shown in FIG. 10, in a three bit-per cell memory device (TLC),”) in a plurality of program loops, (Prakash, [0021]: “During the programming operation, the programming circuit is configured to program memory cells to a first programmed data state by conducting a plurality of programming loops”) at least one of the program loops including a programming pulse (Prakash, “programming pulse”) at a programming voltage, (Prakash, “programming voltage”) a verify operation to verify a first data state, (Prakash, [0005]: “conducting a plurality of programming loops until programming of the first programmed data state is completed. The programming loops include applying a programming pulse to the selected word line,”) and an analog bitscan operation; (Prakash, “bitscan operation”) determining an output of the analog bitscan operation, the output being one of at least three options; (Prakash, [0005]: “conducting a bitscan operation prior to the application of the programming pulse of a next subsequent programming loop.”; [0060]: “For NAND memory cells, a bitscan is an operation that counts a number of memory cells whose threshold voltage has not shifted above a particular verify level for a particular memory state.”; [0060]: “For example, a state S1 bitscan is a count of a number of data state S1 memory cells whose threshold voltages has not shifted above a verify voltage level for data state S1 (see Vv1 in FIGS. 9-11).”; this provides for any number of options) and out of at least three different possible settings, determining setting which data states are to be verified in a subsequent program loop based on the output of the analog bitscan operation. (Prakash, including [0070]: “The control circuits can include a programming circuit configured to perform a program and verify operation for one set of memory cells, wherein the one set of memory cells comprises memory cells assigned to represent one data state among a plurality of data states and memory cells assigned to represent another data state among the plurality of data states; the program and verify operation comprising a plurality of program and verify iterations; and in each program and verify iteration, the programming circuit performs programming for the one word line after which the programming circuit applies a verification signal to the one word line. The control circuits can also include a counting circuit configured to obtain a count of memory cells which pass a verify test for the one data state. The control circuits can also include a determination circuit configured to determine, based on an amount by which the count exceeds a threshold, a particular program and verify iteration among the plurality of program and verify iterations in which to perform a verify test for another data state for the memory cells assigned to represent another data state.”)
Regarding claim 2, Prakash teaches the method as set forth in claim 1, wherein the at least three options for the output of the analog bitscan operation comprise a first output option, a second output option, a third output option, and a fourth output option. (Prakash, FIG. 9-11; Prakash provides for 4 output options, among other numbers of options)
Regarding claim 5, Prakash teaches a method of setting a smart verify programming voltage, comprising the steps of: preparing a memory block that includes a plurality of memory cells that are arranged in a plurality of word lines, (Prakash, [0002]: “In an EEPROM or flash NAND array architecture, memory cells may be arranged in a matrix of rows and columns such that gates of each memory cell are coupled by rows to word lines. The memory cells may be arranged together in strings such that memory cells in a given string are coupled together in series, from source to drain, between a common source line and a common bit line.”) the plurality of word lines including a selected word line; (Prakash, [0005]: “The method includes the step of programming memory cells of a selected word line to a first programmed data state”) programming at least some of the plurality of memory cells of the selected word line to a smart verify voltage (Instant specification describes “smart verify voltage” as “a smart verify voltage Vsv, which is either equal to or lower than a verify voltage for a first programmed data state,”, etc.;) in a plurality of program loops, (Prakash, [0021]: “During the programming operation, the programming circuit is configured to program memory cells to a first programmed data state by conducting a plurality of programming loops”) at least one of the program loops including a programming pulse (Prakash, “programming pulse”) at a programming voltage, (Prakash, “programming voltage”) a verify operation to verify a first data state, (Prakash, [0005]: “conducting a plurality of programming loops until programming of the first programmed data state is completed. The programming loops include applying a programming pulse to the selected word line,”) and an analog bitscan operation; (Prakash, “bitscan operation”) determining an output of the analog bitscan operation, the output being one of at least three options; (Prakash, [0005]: “conducting a bitscan operation prior to the application of the programming pulse of a next subsequent programming loop.”; [0060]: “For NAND memory cells, a bitscan is an operation that counts a number of memory cells whose threshold voltage has not shifted above a particular verify level for a particular memory state.”; [0060]: “For example, a state S1 bitscan is a count of a number of data state S1 memory cells whose threshold voltages has not shifted above a verify voltage level for data state S1 (see Vv1 in FIGS. 9-11).”; this provides for any number of options) and the output of the analog bitscan affecting the setting which of at least three different possible settings of the smart verify programming voltage is chosen, the smart verify programming voltage being an initial programming voltage (Prakash, “initial programming voltage”) when programming other word lines than the selected word line. (Prakash, including [0070]: “The control circuits can include a programming circuit configured to perform a program and verify operation for one set of memory cells, wherein the one set of memory cells comprises memory cells assigned to represent one data state among a plurality of data states…”, also Prakash, [0134])
Regarding claim 6, Prakash teaches the method as set forth in claim 5, wherein between program loops, the method includes the step of increasing the programming voltage by a step size; (Prakash, [0055]: “In one approach, incremental step pulse programming is performed, in which the programming pulse amplitude is increased by a step size in each program loop.”) wherein the step size is a first step size in response to the output of the analog bitscan operation being a first option; and wherein the step size is a second step size that is different than the first step size in response to the output of the analog bitscan operation being a second option. (Prakash, FIGS. 12A and 12B; Prakash, [0119]: “During the first pass, a relatively large programming voltage step size may be used to quickly program the memory cells to the respective lower verify levels. The second pass is depicted in FIG. 12B, and the S1, S2, and S3 data states are programmed from the respective lower distributions 1212, 1214, 1216 to respective final distributions 1202, 1204, 1206 using the nominal higher verify levels Vv1, Vv2, and Vv3, respectively. A relatively small programming voltage step size may be used in the second pass to slowly program the memory cells to the respective final distributions while avoiding a large overshoot. Additional data states may (e.g., the S4-S15 data states of FIG. 11) be also be programmed using the multi-pass programming operation depicted in FIGS. 12A and 12B by following the same procedure.”; also [0120], etc.)
Regarding claim 11, Prakash teaches a memory device, (Prakash, [0001]: “relates to the operation of memory devices”; Prakash, FIG. 1A-6D) comprising: a memory block including a plurality of memory cells that are arranged in a plurality of word lines, (Prakash, [0002]: “In an EEPROM or flash NAND array architecture, memory cells may be arranged in a matrix of rows and columns such that gates of each memory cell are coupled by rows to word lines. The memory cells may be arranged together in strings such that memory cells in a given string are coupled together in series, from source to drain, between a common source line and a common bit line.”) the plurality of word lines including a selected word line; (Prakash, [0005]: “The method includes the step of programming memory cells of a selected word line to a first programmed data state”) circuitry that is configured to program at least some of the plurality of memory cells of the selected word line (Prakash, FIG. 10; [0057]: “As shown in FIG. 10, in a three bit-per cell memory device (TLC),”) in at least one program loop of a programming operation, (Prakash, [0021]: “During the programming operation, the programming circuit is configured to program memory cells to a first programmed data state by conducting a plurality of programming loops”) during the at least one program loop, the circuitry being configured to; apply a programming pulse (Prakash, “programming pulse”) to the selected word line, (Prakash, [0005]: “conducting a plurality of programming loops until programming of the first programmed data state is completed. The programming loops include applying a programming pulse to the selected word line,”) perform a verify operation, (Prakash, [0005]: “conducting a plurality of programming loops until programming of the first programmed data state is completed. The programming loops include applying a programming pulse to the selected word line,”) and perform an analog bitscan operation, (Prakash, “bitscan operation”) determine an output of the analog bitscan operation, the output being one of at least three options, (Prakash, [0005]: “conducting a bitscan operation prior to the application of the programming pulse of a next subsequent programming loop.”; [0060]: “For NAND memory cells, a bitscan is an operation that counts a number of memory cells whose threshold voltage has not shifted above a particular verify level for a particular memory state.”; [0060]: “For example, a state S1 bitscan is a count of a number of data state S1 memory cells whose threshold voltages has not shifted above a verify voltage level for data state S1 (see Vv1 in FIGS. 9-11).”; this provides for any number of options) and control at least one programming parameter based on the output of the analog bitscan operation, (Prakash, including [0070]: “The control circuits can include a programming circuit configured to perform a program and verify operation for one set of memory cells, wherein the one set of memory cells comprises memory cells assigned to represent one data state among a plurality of data states and memory cells assigned to represent another data state among the plurality of data states; the program and verify operation comprising a plurality of program and verify iterations; and in each program and verify iteration, the programming circuit performs programming for the one word line after which the programming circuit applies a verification signal to the one word line. The control circuits can also include a counting circuit configured to obtain a count of memory cells which pass a verify test for the one data state. The control circuits can also include a determination circuit configured to determine, based on an amount by which the count exceeds a threshold, a particular program and verify iteration among the plurality of program and verify iterations in which to perform a verify test for another data state for the memory cells assigned to represent another data state.”) the at least one programming parameter being an early program-verify termination parameter or a smart verify parameter, (Prakash, including [0067]: “A storage region 113 may, for example, be provided for programming parameters. The programming parameters may include a program voltage, a program voltage bias, position parameters indicating positions of memory cells, contact line connector thickness parameters, a verify voltage, and/or the like.”) there being at least three different possible settings for the program-verify termination parameter or for the smart verify parameter to be selected from based on which of the at least three options is the output of the analog bitscan operation. (Prakash provides for at least three of position parameters indicating positions of memory cells, contact line connector thickness parameters, a verify voltage, and/or the like.”)
Regarding claim 12, Prakash teaches the memory device as set forth in claim 11, wherein the at least one programming parameter (Prakash, “programming parameters”) is the early program-verify termination parameter and wherein the circuitry is configured to set which data states are to be verified (Prakash, [0067]: “The
programming parameters may include a program voltage, a program voltage bias, position parameters indicating positions of memory cells, contact line connector thickness parameters, a verify voltage, and/or the like. The position parameters may indicate a position of a memory cell within the entire array of NAND strings”, etc…) in a subsequent program loop based on the output of the analog bitscan operation and is configured to apply at least one blind programming pulse without a subsequent verify operation based on the output of the analog bitscan operation. (Instant disclosure: “These program loops with a programming pulse and no verify are hereinafter referred to as ‘blind pulses.’”; “Prakash, [0063]: “The following disclosure describes techniques for reducing programming time by skipping certain verify and bitscan operations, namely, the verify operations following the last programming pulses required to complete programming of memory cells to some data states. Bitscan operations are skipped for all the programming pulses for all the data states except the first programmed data state. Various other features and benefits are also described below.”)
Regarding claim 13, Prakash teaches the memory device as set forth in claim 12, wherein the at least three options for the output of the analog bitscan operation comprise a first output option, a second output option, a third output option, and a fourth output option. (Prakash, FIG. 9-11; Prakash provides for 4 output options, among other numbers of options)
Regarding claim 16, Prakash teaches the memory device as set forth in claim 11, wherein the at least one programming parameter is the smart verify parameter. (Prakash, [0067]: “The programming parameters may include a program voltage, a program voltage bias, position parameters indicating positions of memory cells, contact line connector thickness parameters, a verify voltage, and/or the like.”)
Regarding claim 17, Prakash teaches the memory device as set forth in claim 16, wherein between program loops, the circuitry is configured to increase the programming voltage by a step size, (Prakash, [0055]: “In one approach, incremental step pulse programming is performed, in which the programming pulse amplitude is increased by a step size in each program loop.”) and wherein the circuitry is further configured to: in response to the output of the analog bitscan operation being a first output option, set the step size at a first size; and in response to the output of the analog bitscan operation being a second output option, set the step size at a second size that is different than the first size. (Prakash, FIGS. 12A and 12B; Prakash, [0119]: “During the first pass, a relatively large programming voltage step size may be used to quickly program the memory cells to the respective lower verify levels. The second pass is depicted in FIG. 12B, and the S1, S2, and S3 data states are programmed from the respective lower distributions 1212, 1214, 1216 to respective final distributions 1202, 1204, 1206 using the nominal higher verify levels Vv1, Vv2, and Vv3, respectively. A relatively small programming voltage step size may be used in the second pass to slowly program the memory cells to the respective final distributions while avoiding a large overshoot. Additional data states may (e.g., the S4-S15 data states of FIG. 11) be also be programmed using the multi-pass programming operation depicted in FIGS. 12A and 12B by following the same procedure.”; also [0120], etc.)
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL J KING whose telephone number is (703)756-1232. The examiner can normally be reached M-F 9am-5pm.
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/DANIEL JOHN KING/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827