DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/ Restriction
2. Applicant’s election without traverse of Invention I, claims 1-5, in the reply filed on 11/28/2025 is acknowledged.
3. Claims 6-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 11/28/2025, as noted above.
Claim Objections
4. Claim 1 is objected to because of the following informalities:
Claim 1, line 8, recites: “a first gate trench formed the interlayer dielectric layer” which should be changed to “a first gate trench formed in the interlayer dielectric layer” for readability.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chu et al. U.S. Patent Application Publication 2021/0399099 A1 (the ‘099 reference).
The reference discloses in Fig. 5 and related text a semiconductor structure as claimed.
Referring to claim 1, the ‘099 reference discloses a semiconductor structure comprising:
a substrate (20, para [15]);
a plurality of composite layers on a portion of the substrate, wherein a composite layer of the plurality of composite layers includes a plurality of channel layers (2080, para [18]) stacked one over another and a second gate trench (~218 (to be filled with gate material 218 of gate structure material 220, para [20])) between two neighboring channel layers (2080);
an interlayer dielectric layer (232, para [19]) formed on a surface of the substrate and surfaces of the plurality of composite layers;
a first gate trench (~220 (to be filled with gate material 220, para [20])) formed in the interlayer dielectric layer (232) and a gate sidewall (interfacial layer 214 and/or gate dielectric layer 216, para [20]) formed on a side surface of the first gate trench (~220), wherein the first gate trench and the gate sidewall (222) cross over a portion of a sidewall and a portion of a top surface of the composite layer, and the first gate trench (~220) communicates with the second gate trench (~218) (because the first gate trench ~220 and the second gate trench ~218 are part of gate structure 220, para [20]);
a gate (218) in the first gate trench (~220) and the second gate trench (~218), the gate (218) and the gate sidewall (214 and/or 216) forming a gate structure (gate structure 220, para [20]);
a doping region (226 and/or 228, para [18]) formed in a channel layer (2080) under the gate sidewall (222); and
a source-drain layer (225S/225D, para [18]) formed in the composite layer on two sides of the gate structure (220).
Referring to claim 2, the reference further discloses an inner sidewall (214 and/or 216, para [20]) formed on a sidewall of the second gate trench (~218) and between two neighboring channel layers (2080).
Referring to claim 3, the reference further discloses that the gate (218) includes:
a gate dielectric layer (216, para [20]) and a gate electrode layer (218, para [20]) formed on a surface of the gate dielectric layer (216), the gate dielectric layer (216) being formed on a surface of the channel layer (2080) exposed by the first gate trench (~220) and the second gate trench (~218) (and note that interfacial layer 214 is not a requirement for the gate to function, para [20]).
Referring to claim 4, for the semiconductor structure detailed above for claim 1, the reference further discloses that a bottom of the gate sidewall (214 and/or 216) is in contact with a surface of the channel layer (2080).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. §103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claim 5 is rejected under 35 U.S.C. §103 as being unpatentable over Chu et al. U.S. Patent Application Publication 2021/0399099 A1 (the ‘099 reference).
Referring to claim 5, the ‘099 reference further discloses that the doping region (226 and/or 228) contains a dopant including N-type or P-type ions (para [19]). Although the reference does not specifically disclose dimensions as claimed, the claimed dimensions (a concentration of a dopant in the doping region ranges from 1E8 atoms/cm3 to 9E15 atoms/cm3) will not support the patentability of subject matter encompassed by the prior art (the ‘099 reference discloses that a concentration of the dopant can be adjusted to control contact resistance, para [18] ) unless there is evidence indicating such dimensions are critical. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation"; MPEP 2144.05.
Conclusion
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TU TU V HO whose telephone number is (571)272-1778. The examiner can normally be reached on Monday to Thursday 6:30 - 15:00, Monday through Thursday.
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02-05-2026
/TU-TU V HO/Primary Examiner, Art Unit 2818