DETAILED ACTION T his office action is in response to application 18/234,387 filed 8/16/2023. Claims 1-11 have been examined. The IDS sent 2/12/2026 has been considered. T he present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 1-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 1, 3, 6, 8-10 recites the limitations m-channel and n-channel without clarifying that m and n are each a positive integer value. Therefore the claim language does not provide sufficient detail to establish the meaning of the terms “m” and “n” therefore the meets and bounds of the claimed elements cannot be established, rendering it indefinite. Examiner suggests applicant amend claim 1 to recite “wherein m is a positive integer value” and “wherein n is a positive integer value” per para [0019] of the instant application among other paras of the instant application. ). Claims 2, 4-5, 7, and 11 are rejected for failing to comply with the written description requirement. These claims depend from base claim 1 that has been rejected and fail to cure the deficiencies of base claim 1. Allowable Subject Matter Claim 5 is objected to but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and resolving any indefinite rejections . Claim 5 recites the limitations ‘ wherein: the computing system further comprises a buffer; the method further comprises recording access data in the buffer; and the memory controller determines that the access event of the application is to be switched from the high performance mode to the low power mode when the buffer is full and the low power m ode is desirable ’ within the context of claim 1. This limitation requires a buffer where data being accessed (where the access of data accessed is related to a n event) is recorded in the buffer which becomes full and the system determines a low power mode is desirable, and in response to these occurrences [(1) the buffer is full, and (2) the system determines the low power mode is desirable] the system channels identified in claim 1 are switched from the high performance mode of m-channels to the low performance mode of n-channels. An updated search failed to identify a teaching , alone or in combination, to teach the above claim limitations. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim s 1-4, 6, 8, and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Nachimuthu ( Nachimuthu et al., US 2014/0143577 A1) in view of Gross (Gross et al., US 10,409,744 B1). Regarding claim 1 , A memory control method for a computing system, ( Nachimuth u [0001] discloses the inventive concepts re directed to computer systems that implement a method for multi-level memory hierarchy. See also Nachimuthu [0064] that discloses it is directed to a method for shutting down memory channels in response to entering a lower power state. ) the computing system comprising a memory controller, ( Nachimuthu [0041] discloses the system is controlled by intelligent power management software such as ACPI that controls the memory, thus is an example of a memory controller . ) a central processing unit (CPU) , ( Nac h imuthu [0004] that discloses the device is tied to a processor (i.e. a CPU).) a random access memory (RAM) , ( Nachimuthu [0003] discloses the memory may be dynamic random access memory or static random access memory.) the memory control method comprising: the memory controller determining if the computing system is in a low power mode; ( Nachimuthu [0063] -[ 0064] discloses the system may enter a low power state where memory channels are disabled ) … the CPU performing page migration to move data in at least one m-channel region of the RAM to at least one n-channel region of the RAM, where m>n; ( Nachimuthu [0063 ] -[0064] discloses when the system enters a low power state to shutdown memory channels the system will move the content of the memory to be shutdown to other memory locations, where the system is converted from a system with m channels to a system with n channels where m>n . Nachimuthu [0075] discloses that memory access is usually performed with the granularity of a memory page, thus the system is performing a page migration. ) and after completing the page migration, the CPU notifying the memory controller completion of the page migration . ( Nachimuthu [0084] discloses after the data is moved to a new physical address, the TEs (logical to physical translation entries) are updated by the ACPI software, thus the CPU notifies the ACPI software managing the channels. ) However, Nachimuthu does not explicitly disclose if the memory controller detects at least one m-channel regions of the RAM has been accessed, the memory controller sending an interrupt to a hypervisor of the CPU . Gross , of a similar field of endeavor, further discloses if the memory controller detects at least one m-channel regions of the RAM has been accessed, the memory controller sending an interrupt to a hypervisor of the CPU; ( Gross col 17 lines 1-17 and col 27 lines 38-44 discloses that a write request may trigger an interrupt, thus the m-channel regions of Nachimuthu that is within a hypervisor may interrupt the CPU of Nachimuthu that may be a virtual machine running on the CPU of Nachimuthu b a sed o n detecting at least on m-channel access. ) Nachimuthu and Gross are in a similar field of endeavor as both relate to managing memory devices in a low power state. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate the interrupt processing of Gross into the solu t ion of Nachimuthu , thus combining prior art elements according to known events to provide predictable results (To inform the system that a transaction that is to be processed has been received using a well-known, well understood , and common technique (interrupts).). Regarding claim 2 , Nachimuthu and Gross teach all of the limitations of claim 1 above. Nachimuthu further teaches wherein the RAM is a dynamic random access m emory. ( Nachimuthu [0003] discloses the memory may be dynamic random access memory or static random access mem ory). Regarding claim 3 , Nachimuthu and Gross teach all of the limitations of claim 1 above. Nachimuthu further teaches further comprising enabling the at least one m-channel region of the RAM. ( Nachimuthu Fig. 6 and para [0091] that discloses the system may enable the channels previously disabled, thus the system enables the system to the previous mode containing m - channels. ) Regarding claim 4 , Nachimuthu and Gross teach all of the limitations of claim 1 above. Nachimuthu further teaches further comprising the memory controller recording access data and physical address in a buffer. ( Examiner notes that a buffer may simply be a memory area. Nachimuthu [0084] discloses after the data is moved to a new physical address, the TEs (logical to physical translation entries) are updated. Thus the system records the access (data) the data moved and the physical address in memory (i.e. the buffer) .) Regarding claim 6 , Nachimuthu and Gross teach all of the limitations of claim 1 above. Nachimuthu further teaches wherein: the CPU performing the page migration to move the data in the at least one m-channel region of the RAM to the at least one n-channel region of the RAM is the CPU performing the page migration to move the data from the physical address of the RAM to the at least one n-channel region of the RAM. ( Nachimuthu [0075] discloses that memory access is usually performed with the granularity of a memory page. Thus in the migration of Nachimuthu [0063] -[ 0064] , the system will migrate data of a physical page in a m-channel memory into a n-channel as detailed in claim 1 which is performed as a page migration.) Regarding claim 8 , Nachimuthu and Gross teach all of the limitations of claim 1 above. Nachimuthu further teaches wherein: the CPU comprises a memory management unit (MMU); (Examiner notes that a memory management unit is a hardware component that performs address translation. Nachimuthu [0075] discloses that the CPU typically has a TLB translation lookaside buffer resident in the CPU that performs physical address translations, thus the CPU of Nachimuth u is an example of a memory management unit.) and the CPU performing the page migration to move the data in the at least one m-channel region of the RAM to the at least one n-channel region of the RAM is the MMU of the CPU performing the page migration to move the data from the at least one m-channel region of the RAM to the at least one n-channel region ( Nachimuthu [0063]-[0064] discloses when the system enters a low power state to shutdown memory channels the system will move the content of the memory to be shutdown to other memory locations, where the system is converted from a system with m channels to a system with n channels where m>n . Nachimuthu [0075] discloses that memory access is usually performed with the granularity of a memory page, thus the system is performing a page migration. ) of the RAM. ( Nachimuthu [0003] discloses the memory may be dynamic random access memory ) Regarding claim 1 0 , Nachimuthu and Gross teach all of the limitations of claim 1 above. Nachimuthu further teaches wherein the at least one n-channel region is outside the at least one m-channel region. ( Nachimuthu [0067] discloses that one region of memory may be reserved for DRAM DIMMS, and a second portion of the memory channels may be reserved for PCMS DIMMS. Nachimuthu [0071] the DRAM DIMM cards may be chosen to enable/disable as DRAM devices are faster and consume more power than PCMS devices. The m-channel region may be composed of both PCMS DIMMS channels and DRAM DIMMS channels and the n-channel region may be compose of the PCMS DIMMS only. Thus the PCMS DIMMS memory channel regions are outside the DRAM DIMM channel regions as they are separate address spaces per Nachimuthu [0069].) Regarding claim 11 , Nachimuthu and Gross teach all of the limitations of claim 1 above. Nachimuthu further teaches wherein the CPU performing the page migration is the hypervisor and a memory management unit of the CPU performing the page migration. ( Nachimuthu [0069] and [0072] -[ 0074] and [0077] discloses the virtual machine monitor running on the computer’s cpu manages the memory and powers down channels and moves the memory using a page mode.) Claim s 7 and 9 a re rejected under 35 U.S.C. 103 as being unpatentable over Nachimuthu ( Nachimuthu et al., US 2014/0143577 A1) in view of Gross (Gross et al., US 10,409,744 B1) as detailed in claim 1 above and further in view of Liu (Liu et al., US 2016/0054947 A1). Regarding claim 7 , Nachimuthu and Gross teach all of the limitations of claim 1 above. However the combination does not explicitly discloses wherein m is 4, and n is 2 . Liu, of a similar field of endeavor, further teaches wherein m is 4, and n is 2. (Liu [Abstract] teaches memory that operations in two separate modes where the second mode contains fewer channels. Liu teaches that the larger channel memory may be a 4-channel memory and the smaller channel memory may be a 2-channel memory. Thus Liu teaches that m=4 and n=2. Examiner notes that Liu uses the terms m-channel and n-channel, however Liu teaches n>n thus has swapped the meaning of the terms when compared to how the terms are used in the instant application . ) Nachimuthu , Gross, and Liu are all in a similar field of endeavor as all relate to managing power consumption for memory devices. Thus it would have been obvious to a person of ordinary skill in the art to incorporate m-channel memory where m=4 and n-channel memory where n=2. Thus combining prior art el e ments according to known device. One would be motivated to do so in order to support quad-channel or dual-channel memory devices (since the lower dual-channel memory devices may be sufficient for mainstream processors and gaming and provide good performance using less power than quad-channel memory that is better suited for high-performance tasks such as intense gaming, and scientific computing. Thus reserving the high power consumption for only those applications that justify its high performance.) Regarding claim 9 , Nachimuthu and Gross teach all of the limitations of claim 1 above. Nachimuthu further teaches wherein the at least one n-channel region is within the at least one m-channel region. ( Liu Fig. 2 and paras [0024] discloses that the memory operating in 4-channel mode may be the same memory that is operated in a 2-channel mode. Thus the n-channel region is within the m-channel region as the two regions are the same region.) The motivation to combine Liu into Nachimuthu and Gross is the same as set forth in claim 7 above. Relevant Art The prior art made of record and not relied upon is : the definition of memory management unit in the Microsoft Dictionary that defines a memory management unit as the hardware that supports the mapping of virtual memory addresses to physical memory addresses. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT JANICE M. GIROUARD whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (469)295-9131 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F 9:30 - 7:30 . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. 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