DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness . Claim s 1 -5 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US PG Pub 2019/0214788) in view of Yu et al. (US PG Pub 2020/0014169) and Ryu et al. (US PG Pub 2017/0179686) . Regarding claim 1, Kang et al. disclose : a substrate (212) (Figs. 11 and 13, [0321], [0322]) ; an adhesive layer (260) coated on the substrate (Fig. 13, [0321], [0322]) ; a VCSEL chip (layers 220, 230, 24 0 , 250) disposed on the adhesive layer and fixed to the adhesive layer and configured to oscillate light or a laser by being supplied with power (Fig. 13, [0307]-[0316]) . Kang et al. do not disclose: a VCSEL array, a polymer coated on the VCSEL chip and the adhesive layer; and an interconnector electrically connected to the VCSEL chip. Yu et al. disclose: a polymer (306) coated on the VCSEL chip (Fig. 12, [0040]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kang by coating a polymer layer on the VCSEL chip and the adhesive layer in order to protect the VCSEL chip. Kang as modified do not disclose: a VCSEL array, an interconnector electrically connected to the VCSEL chip. Ryu et al. disclose: a laser array, interconnectors electrically connected to a laser device (Fig. 4, [0033]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kang as modified by forming an array of VCSELs and also forming interconnectors electrically connected to the VCSEL chip in order to electrically bias the VCSEL chip and to increase the output power of the device . Fig. 11 of Kang Fig. 13 of Kang Fig. 12 of Yu Regarding claim 2, Kang as modified disclose : a first reflection part (one of DBR layer 250 or 220) comprising a plurality of distributed Bragg reflector (DBR) pairs (Kang, Fig. 13, [0275], [0307]-[0316]) ; a second reflection part (the other of DBR layer 250 or 220) comprising a plurality of DBR pairs (Kang, Fig. 13, [0275], [0307]-[0316]) ; a cavity layer (active region 230) that is disposed between the first reflection part and the second reflection part and in which holes that are generated from any one of the first reflection part and the second reflection part and electrons that are generated from the other of the first reflection part and the second reflection part are recombined (Kang, Fig. 13, [0251], [0274], [0275], [0307]-[0316]) ; an oxide layer (aperture region 240) disposed between the cavity layer and the first reflection part or the second reflection part and configured to determine characteristics of a laser to be output and a diameter of an opening (Kang, Fig. 13, [0067], [0330]) ; a first metal layer (215) configured to come into contact with the first reflection part (220) so that power is supplied to the first reflection part (Kang, Fig. 13, [0307]-[0325]) ; a second metal layer (255) configured so that power is supplied to the second reflection part (250) (Kang, Fig. 14, [0334]) ; an etch-stop layer (192) disposed under the second reflection part (220) and configured to prevent damage to the second reflection part in an etch process (Kang, Fig. 11, [0305]) ; and a passivation layer (270) configured to protect the first reflection part, the second reflection part, the cavity layer, the oxide layer, the contact layer, and the etch-stop layer against an outside (Kang, Fig. 14, [0335]) . Kang as modified do not disclose: a contact layer formed within one DBR pair of the second reflection part; second metal layer configured to come into contact with the contact layer . Yu et al. disclose: contact layer (114) formed on a DBR (112) (Fig. 12, [0017]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kang as modified by forming a contact layer within one DBR pair of the second reflection part in order to form an ohmic contact for uniform current injection. Regarding claim 3, Kang as modified do not disclose: wherein the second reflection part comprises more DBR pairs than the first reflection part. However, In accordance with MPEP 2144.05 II, Optimization of Ranges: Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. In the prior art the general conditions are disclosed, a VCSEL array comprising a first DBR (reflection part) and second DBR (reflection part) each with a number of DBR pairs . Therefore, it would have been obvious to one of ordinary skill in the art at the time of the invention to obtain a workable range of values for t he number of DBR pairs for each DBR by routine experimentation. Regarding claim 4, Kang as modified disclose: wherein the contact layer has a mesa structure (contact layer would be a part of mesa structure in the device as modified) (see Fig. 14 of Kang) . Regarding claim 5, Kang as modified disclose: wherein the second metal layer (255) is disposed within the mesa structure and comes into contact with the contact layer (contact layer would be a part of mesa structure and in contact with second metal layer in the device as modified) (see Fig. 14 of Kang, see also the rejection of claim 2) . Regarding claim 12, Kang as modified disclose: a method of manufacturing a vertical cavity surface emitting laser (VCSEL) array, the method comprising: a coating process of coating an adhesive layer on a substrate; a first arrangement process of disposing the VCSEL chip according to claim 2 on a coating layer; a coating process of coating and curing a polymer on the VCSEL chip; a removal process of removing the polymer coated on each metal layer of the VCSEL chip; and a second arrangement process of disposing an interconnector on each metal layer of the VCSEL chip (the apparatus of claim 2 discloses the claimed method, see the rejection of claim 2). Claim s 8-11 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US PG Pub 2019/0214788) in view of Yu et al. (US PG Pub 2020/0014169), Ryu et al. (US PG Pub 2017/0179686) and Joseph et al. (US PG Pub 2011/0148328). Regarding claim 8, Kang as modified do not disclose: wherein the VCSEL chip comprises one or more output parts. Joseph et al. disclose: VCSEL chip comprises one or more output parts (apertures) (Fig. 3, [0060]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kang as modified by forming the VCSEL chip with one or more output parts in order to adjust the output beam profile. Regarding claim 9, Kang as modified disclose: wherein the VCSEL chip has a cross section having a preset shape (square shape for the device of claim 8) . Regarding claim 10, Kang as modified disclose: wherein the preset shape is identical although the preset shape is rotated at a preset angle (square shape is identical when rotated at an angle) . Regarding claim 11, Kang as modified disclose: wherein if the VCSEL chip includes a plurality of output parts, light or a laser having an identical or different wavelength is output from each of the output parts (Joseph, Fig. 3, [0060]) . Allowable Subject Matter Claims 6-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 6 is allowable as the prior art fails to anticipate or render obvious the claimed limitations including “…wherein the etch-stop layer has a mesa structure.” Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yeh et al. (US PG Pub 2003/0032209) disclose: a optoelectronic module comprises one or more VCSELs electrically connected to an IC and optically connected to a fiber optic faceplate. The fiber optic faceplate, comprising a closely packed bundle of optical fibers, permits efficient capture of light from the VCSELs. Precise alignment of the faceplate with respect to the VCSELs is not needed since light not collected by one fiber is captured by another nearby optical fiber. One method of fabricating the module comprises forming substrate layers on both sides of the VCSELs such that features can be formed on the first substrate layer while the second temporary substrate layer provides structural support. The method further comprises forming apertures on the first substrate layer by etching. An etch stop buffer layer positioned between the first substrate layer and the VCSELs protects the VCSELs from being etched in the process. The second temporary substrate layer is removed after the fiber optic faceplate is mounted on the first substrate side. An alternate method of VCSEL fabrication comprises forming an aperture by patterning a dielectric layer above an active layer within the VCSEL. The aperture in the dielectric layer can be formed with a high degree of precisely using conventional patterning techniques. The dielectric layer is part of a current confinement element that concentrates current in an active region. A top DBR can also be formed of multiple layers of dielectric (Abstract). Maeda et al. (US 8,363,687) disclose: a Vertical Cavity Surface Emitting Laser (VCSEL) capable of providing high output of fundamental transverse mode while preventing oscillation of high-order transverse mode is provided. The VCSEL includes a semiconductor layer including an active layer and a current confinement layer, and a transverse mode adjustment section formed on the semiconductor layer. The current confinement layer has a current injection region and a current confinement region. The transverse mode adjustment section has a high reflectance area and a low reflectance area. The high reflectance area is formed in a region including a first opposed region opposing to a center point of the current injection region. A center point of the high reflectance area is arranged in a region different from the first opposed region. The low reflectance area is formed in a region where the high reflectance area is not formed, in an opposed region opposing to the current injection region (Abstract) . Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT XINNING(TOM) NIU whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-1437 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F: 9:30am-6:00pm . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Minsun Harvey can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 571-272-1835 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /XINNING(Tom) NIU/ Primary Examiner, Art Unit 2828