DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in WIPO on June 5, 2023. It is noted, however, that applicant has not filed a certified copy of the PCT/CN2023/098215 application as required by 37 CFR 1.55.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 318A, 704.
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 2-3, 9-10, 14, and 20 are objected to because of the following informalities:
In claim 2, line 4, “PCIe” should be -Peripheral Component Interconnect Express (PCIe)-.
In claim 9, line 4, “PCIe” should be -Peripheral Component Interconnect Express (PCIe)-.
In claim 14, line 2, “the PCIe” should be -a Peripheral Component Interconnect Express (PCIe)-.
In claim 20, line 2, “PCIe” should be -Peripheral Component Interconnect Express (PCIe)-.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 4-8, 11-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Subhash et al. (US 2024/0172398, effective filing date November 22, 2022), hereafter referred to as Subhash’398 in view of Park et al. (US 2023/0007903), hereafter referred to as Park’903.
Referring to independent claim 1, Subhash’398 teaches an apparatus comprising: a printed circuit board (PCB) (typical memory sub-systems are implemented on a PCB and distribute the components on the PCB in a way that minimizes heat build-up on certain components, paragraph 16, lines 4-7); and an M.2 connector (M.2 SSD interface, paragraph 29, lines 16-17) including a socket to receive an M.2 card (memory slot of the M.2 SSD interface, paragraph 30, lines 14-15).
Subhash’398 does not appear to explicitly teach universal flash storage (UFS) signal lines in or on the PCB and coupled with the M.2 connector.
However, Park’903 teaches universal flash storage (UFS) signal lines in or on a PCB (storage controller 1210 transmits command UPIU to UFS device, see figure 5B, step S110 and paragraph 85, lines 1-3; storage controller 1210 may transmit a command UPIU including a write command WR CMD to the first UFS device 1301, see figure 5B, step S110 and paragraph 87, lines 1-3) and coupled with a connector (first slot SL1 may refer to a region, component, or device in which the first UFS device 1301 is mounted; the storage controller 1210 and the first UFS device 1301 may be connected with each other by wire patterns provided in the printed circuit board PCB1, see figure 7C and paragraph 100, lines 3-7).
Subhash’398 and Park’903 are analogous because they are both drawn to the same inventive field of printed circuit boards and flash storage.
Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Subhash’398 and Park’903 before them, to modify the apparatus of Subhash’398 to include the UFS signal lines by incorporating UFS signal lines into the system.
The motivation for doing so would have been to support an operating speed higher than that of a conventional flash memory-based storage device (paragraph 4, lines 5-9).
Therefore, it would have been obvious to combine Subhash’398 and Park’903 to bring about the invention as claimed.
As to claim 4, Subhash’398 teaches the apparatus of claim 1, further comprising: an M.2 card (memory slot of the M.2 SSD interface, paragraph 30, lines 14-15) including a UFS storage device (a Universal Flash Storage (UFS) drive, paragraph 27, lines 7-8).
Note that independent claim 8 contains the corresponding limitations of claim 4. Claim 4 further discloses a system-on-chip (SoC), which is taught by Park’903 (application processor may be implemented with a system on chip (SoC), paragraph 30, lines 8-9).
Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Subhash’398 and Park’903 before them, to modify the apparatus of Subhash’398 to include the system on chip of Park’903 by incorporating internal logic as an SoC.
The motivation for doing so would have been to support an operating speed higher than that of a conventional flash memory-based storage device (paragraph 4, lines 5-9).
As to claim 5, Subhash’398 does not appear to explicitly teach the apparatus of claim 4, wherein: the M.2 card includes a clock buffer to receive a UFS clock signal via one of a plurality of pins of the M.2 connector and drive the UFS clock signal to the UFS storage device.
However, Park’903 teaches wherein: the M.2 card includes a clock buffer (phase-locked loop (PLL) or the like, paragraph 49, lines 12-13) to receive a UFS clock signal via one of a plurality of pins of the M.2 connector (reference dock REF_CLK that is provided from the UFS interface circuit 1400 to the first UFS device 1301, see figure 2 and paragraph 49, lines 1-3) and drive the UFS clock signal to the UFS storage device (first UFS device 1301 may generate clocks of various frequencies from the reference clock REF_CLK provided from the UFS interface circuit 1400, see figure 2 and paragraph 49, lines 9-12).
Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Subhash’398 and Park’903 before them, to modify the apparatus of Subhash’398 to include the system on chip of Park’903 by incorporating internal logic as an SoC.
The motivation for doing so would have been to support an operating speed higher than that of a conventional flash memory-based storage device (paragraph 4, lines 5-9).
Note that claims 11 and 17 contain the corresponding limitations of claim 5 as shown above; therefore, they are rejected using the same reasoning accordingly.
As to claim 6, Subhash’398 does not appear to explicitly teach the apparatus of claim 4, wherein: the M.2 card includes one or more voltage regulators to receive a voltage via the M.2 connector and provide one or more reference voltages to the UFS storage device.
However, Park’903 teaches wherein: the M.2 card includes one or more voltage regulators (regulator 1360, see figure 2 and paragraph 59, line 16) to receive a voltage via the M.2 connector (UFS device 1301 may receive VCC, VCCQ1, VCCQ2, and the like as power supply voltages, see figure 2 and paragraph 59, lines 1-2) and provide one or more reference voltages to the UFS storage device (power supply voltages VCC, VCCQ1, and VCCQ2 may be supplied to respective components of the first UFS device 1301 through the regulator 1360, see figure 2 and paragraph 59, lines 13-16).
Note that claims 12 and 18 contain the corresponding limitations of claim 6 as shown above; therefore, they are rejected by the same reasoning accordingly.
As to claim 7, Subhash’398 does not appear to explicitly teach the apparatus of claim 1, wherein: one or more of the UFS signal lines are coupled with reserved pins of the M.2 connector.
However, Park’903 teaches wherein one or more of the UFS signal lines are coupled with reserved pins (first slot SL1 may include slot pins (or slot terminals) that are electrically connected with the plurality of pins of the UFS card 2000, see figure 7A and paragraph 105, lines 3-5) of the M.2 connector (the connector CN may be a connector configured to support an M.2 interface, see figure 7B and paragraph 101, lines 18-20).
Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Subhash’398 and Park’903 before them, to modify the apparatus of Subhash’398 to include the system on chip of Park’903 by connecting particular pins with signal lines.
The motivation for doing so would have been to support an operating speed higher than that of a conventional flash memory-based storage device (paragraph 4, lines 5-9).
Note that claim 13 contains the corresponding limitations of claim 7 as shown above; therefore, it is rejected using the same reasoning accordingly.
As to claim 14, Subhash’398 does not appear to explicitly teach the system of claim 8, further comprising: a system on a chip (SoC), the SoC including one or both of the UFS controller and the PCIe controller.
However, Park’903 teaches a system on a chip (SoC), the SoC including one or both of the UFS controller and the PCIe controller (host controller 1110 may be one of a plurality of modules included in an application processor; in this case, the application processor may be implemented with a system on chip (SoC), see figure 1 and paragraph 30, lines 5-7).
Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Subhash’398 and Park’903 before them, to modify the apparatus of Subhash’398 to include the system on chip of Park’903 by incorporating internal logic as an SoC.
The motivation for doing so would have been to support an operating speed higher than that of a conventional flash memory-based storage device (paragraph 4, lines 5-9).
As to claim 15, Subhash’398 teaches the system of claim 8, further comprising: one or more of: a display, a battery, and a network interface (computer system 500 can further include a network interface device 508 to communicate over a network 520, see figure 5 and paragraph 85, lines 15-17).
Referring to independent claim 16, Subhash’398 teaches an M.2 universal flash storage (UFS) card comprising: a printed circuit board (PCB) (typical memory sub-systems are implemented on a PCB and distribute the components on the PCB in a way that minimizes heat build-up on certain components, paragraph 16, lines 4-7); an edge to be received by an M.2 connector (edge 324 of the PCB, see figure 3 and paragraph 54, lines 9-10); and a UFS storage device (a Universal Flash Storage (UFS) drive, paragraph 27, lines 7-8).
Subhash’398 does not appear to explicitly teach conductive contacts at the edge to couple with contacts of the M.2 connector; and UFS signal lines between the conductive contacts and the UFS storage device.
However, Park’903 teaches conductive contacts at the edge to couple with contacts of the M.2 connector (connector CN, see figure 7B and paragraph 99, line 11); and UFS signal lines between the conductive contacts and the UFS storage device (first slot SL1 may refer to a region, component, or device in which the first UFS device 1301 is mounted; the storage controller 1210 and the first UFS device 1301 may be connected with each other by wire patterns provided in the printed circuit board PCB1, see figure 7C and paragraph 100, lines 3-7).
Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Subhash’398 and Park’903 before them, to modify the apparatus of Subhash’398 to include the edge connector and UFS signal lines of Park’903 by incorporating UFS signal lines into the system and connecting them to an edge connector on the board.
The motivation for doing so would have been to support an operating speed higher than that of a conventional flash memory-based storage device (paragraph 4, lines 5-9).
As to claim 20, Subhash’398 does not appear to explicitly teach the M.2 UFS card of claim 16, wherein the contacts of the M.2 connector include M.2 PCIe pins.
However, Park’903 teaches wherein the contacts of the M.2 connector include M.2 PCIe pins (number and arrangement of pins included in the connector CN may vary depending on a communication interface between the storage device 1200d and the external host 1100, see figure 7B and paragraph 101, lines 3-6; storage device 1200d may communicate with the external host 1100 through one of interfaces such as Peripheral Component Interconnect Express (PCI-Express), see figure 7B and paragraph 101, lines 6-7).
Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Subhash’398 and Park’903 before them, to modify the M.2 connector of Subhash’398 to include the PCIe pins by configuring specific pins to communicate through a PCIe interface.
The motivation for doing so would have been to support an operating speed higher than that of a conventional flash memory-based storage device (paragraph 4, lines 5-9).
Allowable Subject Matter
Claims 2-3, 9-10, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 2, the prior art of record does not appear to anticipate, explicitly teach, or fairly suggest multiplexer circuitry to select the PCIe data lanes or the UFS data lanes based on an input.
Further, it would not have been obvious to combine the above limitations with the remaining limitations of the claim.
Dhali (US 2023/0042673) discloses adapters that can be configured to accommodate removable SSDs having various form factors such as M.2, U.2, or mSATA, among other form factors, and can support various protocols such as NVMe or SATA protocols, among others. However, the reference does not appear to anticipate or explicitly teach the invention as claimed.
Note that claim 9 contains the corresponding limitations of claim 2 as shown above; therefore, it is held to contain allowable subject matter by the same reasoning accordingly.
As to claim 19, the prior art of record does not anticipate, explicitly teach, or fairly suggest wherein the one or more voltage regulators include one or more low drop-out regulators to receive the M.2 supply voltage and provide multiple UFS reference voltages to the UFS storage device.
Further, it would not have been obvious to combine the above limitations with the remaining limitations of the claim.
Chu et al. (US 2019/0379157) discloses a voltage generation circuit that may generate operation voltages of various levels. However, the reference does not appear to anticipate or explicitly teach the invention as claimed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Dhali (US 2023/0042673) discloses adapters that can be configured to accommodate removable SSDs having various form factors such as M.2, U.2, or mSATA, among other form factors, and can support various protocols such as NVMe or SATA protocols, among others.
Chu et al. (US 2019/0379157) discloses a voltage generation circuit that may generate operation voltages of various levels.
However, the references do not appear to anticipate or explicitly teach the invention as claimed.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN B ROCHE whose telephone number is (571)270-1721. The examiner can normally be reached Monday-Friday, 10:30 - 7.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached at (571)272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.B.R/Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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