The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Current Status of Claims
This action is a response to communication of November 13, 2025. By amendment of November, 2025, the Applicant amended claims 1, 3-5, 11, 13, and 19-20 and canceled claims 6-10, 12, and 14-18. Therefore, claims 1 to 5, 11, 13, and 19- 20 remain active in the application.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 filed November 13, 2025 have been considered but are moot because the new ground of rejection does not rely on at least some of the references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-5, 11, 13, and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (CN115312005) in view of Nakamura et al. (US Patent Publication Application 2012/0249612 A1) and further in view of Okuno et al. (US Patent Publication Application 2013/0135275 A1).
In regard of claim 1, Zhang et al. disclose a display panel, comprising: a plurality of pixel circuit columns, wherein a pixel circuit column of the plurality of pixel circuit columns includes a plurality of pixel circuits and is electrically connected with two data lines (See at least Figure 1 of Zhang et al. illustrating a display panel with a pixel circuit columns (P) electrically connected with two data lines (S1 and S2) as discussed in paragraphs related to Figure 1 of Zhang et al.), and one or both of the two data lines transmits a data signal and a bias signal to a pixel circuit of the plurality of pixel circuits in the pixel circuit column in a time-sharing manner (See Figures 2 and 8, 9 illustrating transmitting of data signal and bias signal in data lines (S1, S2) and bias module (30) providing bias signal to each data lines (S1, S2) ) ensuring that the data voltage signal has sufficient writing time).
However, the reference to Zhang et al. does not specifically provide illustration how each data line transmits both a data signal and a bias signal to a pixel circuit of the plurality of pixel circuits in the pixel circuit column in a time-sharing manner.
In the same field of endeavor, Nakamura et al. disclose a display panel (1, 2) shown in Figure 1 with two data lines (11) which provide a data signal (141) and bias signal (142) in time sharing manner as shown at least in Figure 5 and discussed in paragraphs [0090, 0121, 0142, 0144, 0173] of Nakamura et al.
Furthermore the combination of Zhang et al. and Nakamura et al. does not disclose the display panel wherein the two data lines connected to the pixel circuit column include a first data line and a second data line, and the data signal and the bias signal belong to different signal types, the pixel circuit includes a driving module, a data-writing module, and a bias module, wherein the data-writing module is configured to transmit the data signal to the driving module, and the bias module is configured to transmit the bias signal to the driving module, data-writing modules of pixel circuits in odd-numbered rows in the pixel circuit column are connected to the first data line, and bias modules of the pixel circuits in the odd-numbered rows in the pixel circuit column are connected to the second data line and data-writing modules of pixel circuit in even-numbered rows in the pixel circuit column are connected to the second data line, and bias modules of the pixel circuits in the even-numbered rows in the pixel circuit column are connected to the first data line.
In the same field of endeavor, Okuno et al. disclose the display device illustrated in Figure 8, wherein for each column of pixels provided two data lines (for first column data lines DT1 and DT2) and the bias signal belong to different signal types as discussed in paragraphs [0188, 0302] of Okuno et al. and pixel circuit (PIX1) shown aby Okuno et al. includes data-writing module (M1) and bias module (C1, M1) as illustrate in Figure 9 and discussed in paragraph [032] and data-writing modules of pixel circuits in odd-numbered rows in the pixel circuit column connected to the first data line (DT1) and bias modules connected to the second data line (DT2) and data-writing modules (M1) in the even-numbered rows connected to the second data line (DT2) as shown in Figure 9 of Okuno.
Therefore, it would be obvious for a person skilled in the art at time the invention was filed to make connections of the data-writing modules and bias modules in rows as suggested by Okuno et al. and use transmission of data/bias signals as shown by Nakamura et al. with the display panel of Zhang et al. in order to prevent cross-talk and increase service life of a display panel.
In regard of claim 2, Zhang et al. , Nakamura et al., Okuno et al. further disclose the display panel according to claim 1, wherein: adjacent two pixel circuit columns are connected to different data signal terminals through data lines, and a data signal terminal is configured to provide the data signal (See at least Figures 1-2 of Zhang et al. illustrating that adjacent pixel circuit columns (P) connected to different data lines (S1/S and S2/S) providing data signal).
In regard of claim 3, Zhang et al. , Nakamura et al., Okuno et al. further disclose the display panel according to claim 1, wherein: in a same time period, the first data line and the second data line connected to a same one pixel circuit column transmit signals with different types, first data lines connected to adjacent two pixel circuit columns transmit signals with a same type, and second data lines connected to adjacent two pixel circuit columns transmit signals with a same type (See Figures 6-7 of Zhang et al. illustrating the two data lines (S1, S2) and the data signal Vdata and the second Ibias connected to the same pixel circuit (11) as discussed in paragraphs describing Figures 6-8 of Zhang et al.).
In regard of claim 4, Zhang et al. , Nakamura et al., Okuno et al. further disclose the display panel according to claim 1, further including: a first selection circuit and a second selection circuit, wherein: the two data lines connected to the same pixel circuit column are connected to a data signal terminal through the first selection circuit, and the two data lines connected to the same pixel circuit column are connected to a bias signal terminal through the second selection circuit, and the first selection circuit is configured to transmit the data signal provided by the data signal terminal to a data line in a time-sharing manner, and the second selection circuit is configured to transmit the bias signal provided by the bias signal terminal to a data line in the time-sharing manner (See at least Figure 4 of Zhang et al. illustrating a first selection circuit (T1) and second selection circuit (T2) with two data lines (S1/S, S2/S) connected to the same pixel circuit column (P) through the second selection circuit (T2) as discussed in paragraphs relevant to Figure 4 of Zhang et al.).
In regard of claim 5, Zhang et al. , Nakamura et al., Okuno et al. further disclose the display panel according to claim 4, wherein: the first selection circuit includes a first switch and a second switch, both a first terminal of the first switch and a first terminal of the second switch are connected to the data signal terminal, a second terminal of the first switch is connected to the first data line, and a second terminal of the second switch is connected to the second data line, the second selection circuit includes a third switch and a fourth switch, both a first terminal of the third switch and a first terminal of the fourth switch are connected to the bias signal terminal, a second terminal of the third switch is connected to the first data line, and a second terminal of the fourth switch is connected to the second data line, the first switch and the fourth switch are simultaneously turned on or off under control of a first control signal line, and the second switch and the third switch are simultaneously turned on or off under control of a second control signal line, and the first switch and the second switch are sequentially turned on or off under the control of the first control signal line and the second control signal line, respectively (See at least Figure 10 of Zhang et al. illustrating the first selection circuit including the first switch (T1) and second switch (T3) and second selection circuit (T2) and second switch (T4) as discussed in paragraphs relevant to Figure 10).
In regard of claim 11, Zhang et al., Nakamura et al. and Okuno et al. further disclose the display panel according to claim 1, wherein: each pixel circuit in the pixel circuit column is electrically connected with the first data line and the second data line (See at least Figure 2 of Zhang et al. illustrating a pixel (P) connected to the first data line (S1/S) and second data line (S2/S)).
In regard of claim 13, Zhang et al., Nakamura et al. and Okuno et al. further disclose the display panel according to claim 1, wherein: during a time period of displaying one frame, a working process of the pixel circuit includes a data-writing stage, and the data-writing stage includes a data-writing sub-stage and a first bias sub-stage, in the data-writing sub-stage, the driving module of the pixel circuit is written with the data signal, and in the first bias sub-stage, the driving module of the pixel circuit is written with the bias signal, and in the data-writing sub-stage, control signals on the first control signal line and the second control signal line are sequentially in a turned-on level, wherein: the first bias sub-stage occurs after the data-writing sub-stage, and the first bias sub-stage of the pixel circuit in the m.sup.th row and the data-writing sub-stage of the pixel circuit in the (m+2).sup.th row at least partially overlap in time, or the first bias sub-stage occurs before the data-writing sub-stage, and the data-writing sub-stage of the pixel circuit in the n.sup.th row and the first bias sub-stage of the pixel circuit in the (n+2).sup.th row at least partially overlap in time, wherein both m and n are integer greater than zero (See Figure 7 of Okuno et al. illustrating one frame time period when the pixel is working illustrating data write operation in several sub-stages as discussed in paragraphs [0245-0247]).
In regard of claim 19, Zhang et al., Nakamura et al. and Okuno et al. further disclose the display panel according to claim 13, wherein: a working process of the pixel circuit further includes a holding stage, wherein the holding stage includes at least one second bias sub-stage, during a second bias sub-stage of the at least one second bias sub-stage, the driving module of the pixel circuit is written with the bias signal, and a data signal terminal connected to the data line is in a floating state or is configured to provide the bias signal (See at least Figures 6-7 of Zhang et al. illustrating the pixel circuit capable to do holding stage in capacitor (C) during second bias sub-state as shown in timing diagram in Fig. 8 and discussed in descriptive paragraphs).
In regard of claim 20, Zhang et al., Nakamura et al. and Okuno et al. further disclose a display device, comprising: a display panel, the display panel including: a plurality of pixel circuit columns, wherein a pixel circuit column of the plurality of pixel circuit columns includes a plurality of pixel circuits and is electrically connected with two data lines, and each of the two data lines transmits both a data signal and a bias signal to a pixel circuit of the plurality of pixel circuits in the pixel circuit column in a time-sharing manner, wherein the two data lines connected to the pixel circuit column include a first data line and a second data line, and the data signal and the bias signal belong to different signal types, the pixel circuit includes a driving module, a data-writing module, and a bias module, wherein the data-writing module is configured to transmit the data signal to the driving module, and the bias module is configured to transmit the bias signal to the driving module, data-writing modules of pixel circuits in odd-numbered rows in the pixel circuit column are connected to the first data line, and bias modules of the pixel circuits in the odd-numbered rows in the pixel circuit column are connected to the second data line and data-writing modules of pixel circuit in even-numbered rows in the pixel circuit column are connected to the second data line, and bias modules of the pixel circuits in the even-numbered rows in the pixel circuit column are connected to the first data line. (See rejection of claim 1 provided above).
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Olga V. Merkoulova whose telephone number is ((571)270-7796. The examiner can normally be reached on Mon-Fri. from 7:30-5:00.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's Supervisor, LunYi Lao can be reached on (571) 272-7671. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/OLGA V MERKOULOVA/Primary Examiner, Art Unit 2621
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