DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
I. REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9, 11-17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Partsch (US Pub.: 2024/0394178) in view of Yoshihara et al. (US Pub.: 2023/0195314).
As per claim 1, Partsch teaches/suggests a memory module comprising: a plurality of dynamic random access memory (DRAM) devices, each of the plurality of DRAM devices operating accordingly; and operating with each of the plurality of DRAM devices (Fig. 1; [0013]-[0028]; and [0040]).
Partsch do not teach the memory module comprising: including four slices; and a memory channel including four pseudo channels, each of the four pseudo channels including a corresponding slice of each.
Yoshihara teaches/suggests a module comprising: including four slices; and a memory channel including four pseudo channels, each of the four pseudo channels including a corresponding slice of each (Fig. 1(a)-2(b); and [0039]-[0047]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Yoshihara’s channels into Partsch’s module for the benefit of implementing a high bandwidth access (Yoshihara, [0031]) to obtain the invention as specified in claim 1.
As per claim 2, Partsch and Yoshihara teach/suggest all the claimed features of claim 1 above, where Partsch and Yoshihara further teach/suggest the memory module comprising wherein: the plurality of DRAM devices include a plurality of data devices and at least one error code correction (ECC) device; wherein each of the four pseudo channels include a corresponding slice from each of the plurality of data devices and from the at least one ECC device (Partsch, Fig. 1-2; [0013]-[0029]; [0040]; and Yoshihara, Fig. 1(a)-2(b); [0039]-[0047]).
As per claim 3, Partsch and Yoshihara teach/suggest all the claimed features of claim 1 above, where Partsch and Yoshihara further teach/suggest the memory module comprising wherein: each of the plurality of DRAM devices includes input/output (I/O) interface circuitry to couple with at least one clock signal, at least one command (CA) bus, at least one data strobe signal, and a data bus; and wherein each of the slices includes a plurality of data lanes to couple with the data bus (Partsch, Fig. 1-2; [0013]-[0030]; [0040]; and Yoshihara, Fig. 1(a)-2(b); [0039]-[0047]).
As per claim 4, Partsch and Yoshihara teach/suggest all the claimed features of claim 3 above, where Partsch and Yoshihara further teach/suggest the memory module comprising wherein: each of the slices is configurable to enable 2 or 4 data lanes (Partsch, Fig. 1-2; [0013]-[0030]; [0040]; and Yoshihara, Fig. 1(a)-2(b); [0039]-[0047]).
As per claim 5, Partsch and Yoshihara teach/suggest all the claimed features of claim 3 above, where Partsch and Yoshihara further teach/suggest the memory module comprising wherein: the I/O interface circuitry of each of the plurality of DRAM devices is to couple with two CA buses; and wherein two of the four slices of each of the plurality of DRAM devices share a CA bus (Partsch, Fig. 1-2; [0013]-[0030]; [0040]; and Yoshihara, Fig. 1(a)-2(b); [0039]-[0047]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references would further teach/suggest the above claimed features.
As per claim 6, Partsch and Yoshihara teach/suggest all the claimed features of claim 3 above, where Partsch and Yoshihara further teach/suggest the memory module comprising wherein: the I/O interface circuitry of each of the plurality of DRAM devices is to couple with two data strobe signal lines; and wherein two of the four slices of each of the plurality of DRAM devices share a data strobe (Partsch, Fig. 1-2; [0013]-[0030]; [0040]; and Yoshihara, Fig. 1(a)-2(b); [0039]-[0047]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references would further teach/suggest the above claimed features.
As per claim 7, Partsch and Yoshihara teach/suggest all the claimed features of claim 1 above, where Partsch and Yoshihara further teach/suggest the memory module comprising wherein: two of the four slices of each of the plurality of DRAM devices share one of those slice's data lanes (Partsch, Fig. 1-2; [0013]-[0030]; [0040]; and Yoshihara, Fig. 1(a)-2(b); [0039]-[0047]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references would further teach/suggest the above claimed features.
As per claim 8, Partsch and Yoshihara teach/suggest all the claimed features of claim 1 above, where Partsch and Yoshihara further teach/suggest the memory module comprising wherein: each of the plurality of DRAM devices includes circuitry to: for each of the slices, transmit or receive data over a burst (Partsch, Fig. 1-2; [0013]-[0030]; [0040]; and Yoshihara, Fig. 1(a)-2(b); [0039]-[0047]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references would further teach/suggest the above claimed features.
As per claim 9, Partsch and Yoshihara teach/suggest all the claimed features of claim 1 above, where Partsch and Yoshihara further teach/suggest the memory module comprising wherein: the memory module includes a stacked memory module (Partsch, Fig. 1-2; [0013]-[0030]; [0040]; and Yoshihara, Fig. 1(a)-2(b); [0039]-[0047]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references would further teach/suggest the above claimed features.
As per claim 11, Partsch teaches/suggests a memory module comprising: a plurality of dynamic random access memory (DRAM) devices, each of the plurality of DRAM devices operating accordingly; and operating with memory of the plurality of DRAM devices having the number of DRAM devices (Fig. 1; [0013]-[0028]; and [0040]).
Partsch do not teach the memory module comprising: including four independent slices; and a memory channel including four pseudo channels, each of the four pseudo channels including a number of slices equal to the number devices.
Yoshihara teaches/suggests a module comprising: including four independent slices; and a memory channel including four pseudo channels, each of the four pseudo channels including a number of slices equal to the number devices (Fig. 1(a)-2(b); and [0039]-[0047]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Yoshihara’s channels into Partsch’s module for the benefit of implementing a high bandwidth access (Yoshihara, [0031]) to obtain the invention as specified in claim 11.
As per claim 12, Partsch and Yoshihara teach/suggest all the claimed features of claim 11 above, where Partsch and Yoshihara further teach/suggest the memory module comprising wherein: each of the four pseudo channels includes four slices from a single one of the plurality of DRAM devices (Partsch, Fig. 1-2; [0013]-[0030]; [0040]; and Yoshihara, Fig. 1(a)-2(b); [0039]-[0047]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references would further teach/suggest the above claimed features.
As per claim 13, Partsch and Yoshihara teach/suggest all the claimed features of claim 11 above, where Partsch and Yoshihara further teach/suggest the memory module comprising wherein: each of the four pseudo channels includes one slice from each of the plurality of DRAM devices (Partsch, Fig. 1-2; [0013]-[0030]; [0040]; and Yoshihara, Fig. 1(a)-2(b); [0039]-[0047]).
As per claim 14, Partsch and Yoshihara teach/suggest all the claimed features of claim 11 above, where Partsch and Yoshihara further teach/suggest the memory module comprising wherein: the plurality of DRAM devices include a plurality of data devices and at least one error code correction (ECC) device; wherein each of the four pseudo channels include a corresponding slice from each of the plurality of data devices and from the at least one ECC device (Partsch, Fig. 1-2; [0013]-[0030]; [0040]; and Yoshihara, Fig. 1(a)-2(b); [0039]-[0047]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references would further teach/suggest the above claimed features.
As per claims 15, claim 15 is rejected in accordance to the same rational and reasoning as the above rejection of claim 1, where Partsch and Yoshihara further teach/suggest the system comprising: a processor; and memory coupled with the processor, the memory operating accordingly (Partsch, Fig. 1; [0013]-[0028]; [0040]; and Yoshihara, Fig. 1(a)-2(b); [0039]-[0047]).
As per claim 16, Partsch and Yoshihara teach/suggest all the claimed features of claim 15 above, where Partsch and Yoshihara further teach/suggest the system comprising wherein: the plurality of DRAM devices include a plurality of data devices and at least one error code correction (ECC) device; wherein each of the four pseudo channels include a corresponding slice from each of the plurality of data devices and from the at least one ECC device (Partsch, Fig. 1-2; [0013]-[0030]; [0040]; and Yoshihara, Fig. 1(a)-2(b); [0039]-[0047]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references would further teach/suggest the above claimed features.
As per claim 17, Partsch and Yoshihara teach/suggest all the claimed features of claim 15 above, where Partsch and Yoshihara further teach/suggest the system comprising wherein: each of the plurality of DRAM devices includes input/output (I/O) interface circuitry to couple with at least one clock signal, at least one command (CA) bus, at least one data strobe signal, and a data bus; and wherein each of the slices includes a plurality of data lanes to couple with the data bus (Partsch, Fig. 1-2; [0013]-[0030]; [0040]; and Yoshihara, Fig. 1(a)-2(b); [0039]-[0047]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references would further teach/suggest the above claimed features.
As per claim 20, Partsch and Yoshihara teach/suggest all the claimed features of claim 15 above, where Partsch and Yoshihara further teach/suggest the system further comprising one or more of: a memory controller, a power supply, and a display (Partsch, Fig. 1-2; [0013]-[0030]; [0040]; and Yoshihara, Fig. 1(a)-2(b); [0039]-[0047]).
Claims 10 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Partsch (US Pub.: 2024/0394178) in view of Yoshihara et al. (US Pub.: 2023/0195314) as applied to claims 9 and 15 above, and further in view of KIM (US Pub.: 2020/0227386).
As per claim 10, Partsch and Yoshihara teach/suggest all the claimed features of claim 9 above, where Partsch and Yoshihara further teach/suggest the memory module comprising wherein: the stacked memory module including the plurality of DRAM devices (Partsch, Fig. 1-2; [0013]-[0030]; [0040]; and Yoshihara, Fig. 1(a)-2(b); [0039]-[0047]), but Partsch and Yoshihara do not teach the memory module comprising: includes two or more packages, the two or more packages including devices.
KIM teach/suggest a memory module comprising: includes two or more packages, the two or more packages including devices (Fig. 1A-1B; [0018]-[0026]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include KIM’s package architecture into Partsch and Yoshihara’s module for the benefit of reducing overall footprint, enhancing electrical performance, and decreasing signal loss (KIM, [0013]) to obtain the invention as specified in claim 10.
As per claim 18, Partsch and Yoshihara teach/suggest all the claimed features of claim 15 above, where Partsch and Yoshihara further teach/suggest the system comprising wherein: the memory including the plurality of DRAM devices (Partsch, Fig. 1-2; [0013]-[0030]; [0040]; and Yoshihara, Fig. 1(a)-2(b); [0039]-[0047]), but Partsch and Yoshihara do not teach the system comprising: includes a plurality of stacked memory packages.
KIM teach/suggest a system comprising: includes a plurality of stacked memory packages (Fig. 1A-1B; and [0018]-[0026]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include KIM’s package architecture into Partsch and Yoshihara’s system for the benefit of reducing overall footprint, enhancing electrical performance, and decreasing signal loss (KIM, [0013]) to obtain the invention as specified in claim 18.
As per claim 19, Partsch, Yoshihara and KIM teach/suggest all the claimed features of claim 18 above, where Partsch, Yoshihara and KIM further teach/suggest the system comprising wherein: the plurality of stacked memory packages include at least two packages, wherein the memory channel includes the at least two packages (Partsch, Fig. 1-2; [0013]-[0030]; [0040]; Yoshihara, Fig. 1(a)-2(b); [0039]-[0047]; and KIM, Fig. 1A-1B; [0018]-[0026]).
III. CLOSING COMMENTS
CONCLUSION
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-20 have received a first action on the merits and are subject of a first action non-final.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN KUAN LEE whose telephone number is (571)272-0671. The examiner can normally be reached Monday-Friday.
IMPORTANT NOTE
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHUN KUAN LEE/Primary Examiner
Art Unit 2181 September 27, 2026
