Notice of Pre-AIA or AIA Status
The present application, filed after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings Objection
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, a second glass layer physically coupled with and below the first glass layer (as recited in claim 18) must be shown or canceled from the claim. No new matter may be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objection
Claim 20 is objected to because line 1 recites "in" instead of "on" (note claim 19 line 5).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2008/0044127 A1.
Claim 1: '127 discloses an apparatus comprising (see mainly fig. 8; some elements are in common with earlier figures and are further described therewith):
a glass layer 3 ([0035]) having a first side (lower side in fig. 8) and a second side (upper side) opposite the first side, wherein the glass layer is a solid glass layer;
a cavity (space within 3 occupied by optoelectronic component 4) in the glass layer, the cavity extending from the first side of the glass layer;
a photonics integrated circuit (PIC) die 4 in the cavity;
a compute die 13' (processor module) on the first side of the glass layer and on at least a portion of the PIC die, wherein the PIC die is electrically coupled with the compute die (at least by portions of 21', 22, 9'); and
wherein the PIC die is optically coupled with the glass layer (particularly, optically coupled with a waveguide 6 formed in glass layer 3).
Claim 4: The PIC die 4 is electrically coupled with the compute die 13' through the at least a portion of the PIC die.
Claims 1, 4, 6-7, and 10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2024/0353614 A1.
Claim 1: '614 discloses an apparatus comprising (see mainly fig. 2A):
a glass layer 102 having a first side (upper side in fig. 2A) and a second side (lower side) opposite the first side, wherein the glass layer is a solid glass layer;
a cavity ('614 calls cavities "recesses", [0058]) in the glass layer, the cavity extending from the first side of the glass layer;
a photonics integrated circuit (PIC) die 120 in the cavity;
a compute die 131 ("compute chiplet") on the first side of the glass layer and on at least a portion of the PIC die, wherein the PIC die is electrically coupled with the compute die ([0066]-[0067]); and
wherein the PIC die is optically coupled with the glass layer (particularly, optically coupled with a waveguide 106 of the glass layer, note also photonic signal 111, [0055]).
Claim 4: The PIC die is electrically coupled with the compute die through the at least a portion of the PIC die ([0066]-[0067]).
Claim 6: The compute die 131 is a first compute die; and further comprising: a second compute die 130 on the first side of the glass layer and on the PIC die, wherein the PIC die is electrically coupled with the second compute die.
Claim 7: The first compute die 131 and the second compute die 130 are optically or electronically coupled with each other through the PIC die (schematically depicted by a └─┘shaped trace in PIC 120 in fig. 2A).
Claim 10: The PIC die includes a selected one or more of: a photonics transmission driver circuitry or transimpedance amplifier receiver circuitry, or wherein the compute die includes a selected one or more of: a photonics transmission driver circuitry or transimpedance amplifier receiver circuitry ([0066]).
Allowable Subject Matter
Claims 12-19 are allowed. Claim 20 would be allowable if it is amended to overcome the informality objection above. Claims 2-3, 5, 8-9, and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of claim 1 and all applicable intervening claims.
The applied references do not disclose or suggest the further features set forth in claims 2-3, 5, 8-9, or 11 in combination with the entire apparatus of claim 1. As to independent claims 12 and 19, the applied references do not disclose or suggest at least the recited photonic wire bond optically coupled with the PIC die and the glass layer or a waveguide in the glass layer, in combination with all the other recited features or steps.
Conclusion
The additional references listed on the attached 892 form are considered generally relevant to the subject matter of this application. US 2016/0216445 A1 (figs. 1 and 5) and US 2021/0271020 A1 (fig. 22A) are close to claim 1 but do not appear to disclose that the PIC die is optically coupled with the glass layer. Several of the other cited references disclose examples of photonic wire bonds or other multi-chip assemblies.
Contact Information
Any inquiry concerning this communication should be directed to Mike Stahl at 571-272-2360. If attempts to reach the examiner by telephone are unsuccessful the examiner’s supervisor Uyen-Chau Le can be reached at 571-272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Michael Stahl/Primary Examiner, Art Unit 2874
