DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, drawn to a semiconductor device, claims 1-10 in the reply filed on 11/25/2025 is acknowledged. Examiner indicated in error that claims 1 – 14 are drawn to a semiconductor device, and claims 15 - 20. drawn to a method. However, claims 1-10 are drawn to a semiconductor device and claims 1-10 are examined. All method claims are withdrawn from consideration.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. 20120070944.
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Regarding claim 1, fig. 16 of Kim discloses a memory device comprising:
a memory array region (CAR/WCTR);
a dielectric 134 disposed in the memory array region;
a digit line contact WPLG disposed in the dielectric;
a digit line GWL coupled to the digit line contact by at most one barrier region BPLG on the dielectric, the digit line GWL having a metal composition (see par [0226] - a metallic material);
a transistor (see C/P region and par [0061] - peripheral transistors) in a periphery to the memory array region;
a metal contact GWL (par [0226] - a metallic material) coupled to the transistor, the metal contact having the metal composition of the digit line (a metallic material); and
one or more metal barrier regions BPLG/PPLG/WIL above a metal gate 22 (par [0061] a metallic material) of the transistor, coupling the transistor to the metal contact GWL, the one or more metal barrier regions arranged as a unit on and directly contacting the metal gate and directly contacting the metal contact.
Regarding claim 3, par [0226] of Kim discloses wherein the metal composition includes tungsten.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 4-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kim.
Regarding claim 2, Kim discloses claim 1, but does not disclose wherein the digit line has a thickness equal to a thickness of the metal contact.
However, par [0226] … The contact pads BLPAD may be formed during the formation of the interconnection lines WIL and GWL.
As such it would have been obvious to form a device of Kim comprising wherein the digit line has a thickness equal to a thickness of the metal contact in order to use the same processing steps.
Regarding claim 4, Kim disclose claim 1, Kim discloses wherein the at most one barrier region includes metal nitride (par[0173]) extending above (BPLG which is above 134) and from a top level of the dielectric, and the one or more metal barrier regions include tungsten (par [0173]).
However. Par [0205] of Kim discloses that the vertical conductive pattern 156 may be formed of a metallic material (e.g., tungsten). In some embodiments, the vertical conductive pattern 156 may further include a barrier metal layer (e.g., metal nitride) or a silicide layer.
As such it would have been obvious to form a device comprising wherein the at most one barrier region includes tungsten silicide extending above and from a top level of the dielectric, and the one or more metal barrier regions include tungsten silicon nitride and tungsten silicide in order to have a desire resistance.
Regarding claim 5, Kim does not disclose wherein the tungsten silicide extends above the top level of the dielectric by about 3 nm and the one or more metal barrier regions combined extends above a top level of the metal gate by about 6 nm.
In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
As such it would have been obvious to form a device of Kim wherein the tungsten silicide extends above the top level of the dielectric by about 3 nm and the one or more metal barrier regions combined extends above a top level of the metal gate by about 6 nm in order to meet the applicant’s design.
Regarding claim 6, par [0226] of Kim discloses wherein the digit line is a tungsten digit line without a barrier region above a top level of the dielectric coupling the tungsten digit line to the digit line contact.
Kim does not disclose that the one or more metal barrier regions include tungsten silicon nitride contacting the metal gate and the metal contact.
However. Par [0205] of Kim discloses that the vertical conductive pattern 156 may be formed of a metallic material (e.g., tungsten). In some embodiments, the vertical conductive pattern 156 may further include a barrier metal layer (e.g., metal nitride) or a silicide layer.
As such it would have been obvious to form a device comprising wherein the one or more metal barrier regions include tungsten silicon nitride contacting the metal gate and the metal contact in order to have a desire resistance.
Regarding claim 7, Kim does not disclose of wherein the tungsten silicon nitride has a thickness of 3 nm.
In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
As such it would have been obvious to form a device of Kim of wherein the tungsten silicon nitride has a thickness of 3 nm in order to meet the applicant’s design.
Regarding claim 8, Kim discloses claim 1. Kim does not disclose of wherein a step height between a top level of the metal contact on the transistor in the periphery to a top level of the digit line in the memory array region is about 12 nm.
In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
As such it would have been obvious to form a device of Kim of wherein a step height between a top level of the metal contact on the transistor in the periphery to a top level of the digit line in the memory array region is about 12 nm in order to meet the applicant’s design.
Regarding claim 9, it would have been obvious to form a device of Kim comprising wherein the transistor is a transistor of a complementary metal oxide semiconductor (CMOS) device in order to have low power consumption.
Regarding claim 10, it would have been obvious to form a device comprising wherein the metal gate is a high-k metal gate in order to reduce leakage current and enable continued transistor scaling.
Conclusion
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/VONGSAVANH SENGDARA/Primary Examiner, Art Unit 2893