Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending in this office action.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on August 22, 2023, is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Smith et al. (U.S. Patent Pub. No. 2015/0121086).
Regarding claim 1, Smith et al. teaches an integrated circuit comprising: a first cryptographic module that enables debugging of the first cryptographic module, wherein the first cryptographic module comprises a first logic block (paragraph 0096); and a second cryptographic module that disables all debugging of the second cryptographic module, wherein the second cryptographic module comprises the first logic block (paragraph 0097).
Regarding claim 2, Smith et al. teaches wherein the first cryptographic module further comprises a first persistent storage block in the integrated circuit, and wherein the second cryptographic module further comprises a second persistent storage block in the integrated circuit that is non-overlapping with the first persistent storage block (fig. 3, ref. num 314 and 364).
Regarding claim 3, Smith et al. teaches wherein the first cryptographic module further comprises a second logic block, and wherein the second cryptographic module further comprises the second logic block (paragraph 0078).
Regarding claim 4, Smith et al. teaches wherein the first cryptographic module is implemented by a first firmware image, and wherein the second cryptographic module is implemented by a second firmware image (paragraph 0082 and 0087).
Regarding claim 5, Smith et al. teaches wherein the integrated circuit loads a firmware image for only one of the first cryptographic module or the second cryptographic module into the integrated circuit in response to a flag (paragraph 0095).
Regarding claim 6, Smith et al. teaches wherein the first cryptographic module permits a user to debug the first logic block using a debug interface that is within a first logical boundary of the first cryptographic module, and wherein a second logical boundary of the second cryptographic module excludes the debug interface (paragraph 0062).
Regarding claim 7, Smith et al. teaches wherein the first cryptographic module is compliant with Security Level 1 of Federal Information Processing Standards (paragraph 0004).
Regarding claim 8, Smith et al. teaches wherein the second cryptographic module is compliant with Security Level 2 of Federal Information Processing Standards (paragraph 0004).
Regarding claim 9, Smith et al. teaches wherein the integrated circuit is a configurable logic integrated circuit, and wherein the first logic block comprises configurable logic circuits (paragraph 0094).
Regarding claim 10, Smith et al. teaches a method comprising: loading in an electronic device a first firmware image of a first cryptographic module that allows debugging of the first cryptographic module in response to a flag having a first value (paragraph 0096); and loading in the electronic device a second firmware image of a second cryptographic module that prevents debugging of the second cryptographic module in response to the flag having a second value (paragraph 0097).
Regarding claim 11, Smith et al. teaches wherein the first cryptographic module comprises a first functional block in the electronic device, and wherein the second cryptographic module comprises the first functional block (paragraph 0078).
Regarding claim 12, Smith et al. teaches wherein the first cryptographic module further comprises a second functional block in the electronic device, and wherein the second cryptographic module further comprises the second functional block (paragraph 0078).
Regarding claim 13, Smith et al. teaches wherein the first cryptographic module further comprises a first persistent storage block in the electronic device, and wherein the second cryptographic module further comprises a second persistent storage block in the electronic device (fig. 3, ref. num 314 and 364).
Regarding claim 14, Smith et al. teaches further comprising: storing first sensitive security parameters in a first non-volatile storage block in the electronic device for the first cryptographic module if the first firmware image is loaded in the electronic device; and storing second sensitive security parameters in a second non-volatile storage block in the electronic device for the second cryptographic module if the second firmware image is loaded in the electronic device (paragraph 0089).
Regarding claim 15, Smith et al. teaches wherein the second cryptographic module performs a same set of logical functions that are performed by the first cryptographic module (paragraph 0158).
Regarding claim 16, Smith et al. teaches wherein the first firmware image or the second firmware image is loaded in the electronic device only during boot of the electronic device (paragraph 0131).
Regarding claim 17, Smith et al. teaches a non-transitory computer readable storage medium comprising computer readable instructions stored thereon for causing an integrated circuit to: load a first firmware image for a first cryptographic module that permits a user of the integrated circuit to debug the first cryptographic module (paragraph 0096); and load a second firmware image for a second cryptographic module that blocks the user from performing any debugging functions on the second cryptographic module, wherein a logical boundary of each of the first cryptographic module and the second cryptographic module comprises a functional block in the integrated circuit (paragraph 0097).
Regarding claim 18, Smith et al. teaches wherein the computer readable instructions further cause the integrated circuit to load only one of the first firmware image or the second firmware image that is selected based on a value of a flag (paragraph 0163).
Regarding claim 19, Smith et al. teaches wherein the first cryptographic module comprises first persistent memory in the integrated circuit, and wherein the second cryptographic module comprises second persistent memory in the integrated circuit that is non-overlapping with the first persistent memory (fig. 3, ref. num 314 and 364).
Regarding claim 20, Smith et al. teaches wherein the first cryptographic module comprises a debug interface block (paragraph 0022).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON HOFFMAN whose telephone number is (571)272-3863. The examiner can normally be reached Monday-Friday 8:30AM-5:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeffrey Pwu can be reached at (571)272-6798. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRANDON HOFFMAN/Primary Examiner, Art Unit 2433
