DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (Liu) (US 11,908,102 B2) in view of Appalaraju et al. (Appalaraju) (US 10,467,526 B1).
Regarding claim 1, Liu discloses a system, comprising:
a storage medium; and
a processor (e.g., FIG. 15 is a schematic block diagram of an image processing device provided by at least one embodiment of the present disclosure, figure 15, paragraph 23) comprising circuitry configured to:
generate, from a neural network for processing a plurality of inputs corresponding to a set of color channels in instances of input image data (e.g., FIG. 5 is an exemplary flowchart corresponding to step S200 shown in FIG. 4, FIG. 6A is a schematic block diagram of an architecture of a generative network corresponding to the image processing method shown in FIG. 4 provided by at least one embodiment of the present disclosure, paragraph 60), a sub-network for processing a reduced set of the plurality of inputs that includes fewer color channels than the set of color channels to be processed by the neural network (e.g., As shown in FIG. 1, the CNN includes an input layer 101, a hidden layer 102, and an output layer 103. The input layer 101 has 4 inputs; the hidden layer 102 has 3 outputs; the output layer 103 has 2 outputs; and the CNN finally outputs 2 images, paragraph 32).
Liu does not specifically disclose store the sub-network in the storage medium.
Appalaraju discloses store the sub-network in the storage medium (e.g., In one embodiment, a collection of images (or image pairs) as well as intermediate and/or final results of analysis of the images (such as the kinds of vectors produced using neural network models discussed above) may be stored at a storage service 823, paragraph 88).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the invention to have modified Liu to include store the sub-network in the storage medium as taught by Appalaraju. It would have been obvious to one of ordinary skill in the art at the time of the invention to have modified Liu by the teaching of Appalaraju to use for particular application.
Regarding claim 2, Liu discloses wherein the processor is configured to generate, from the neural network, an additional sub-network for processing an additional set of color channels that includes: fewer color channels than the set of color channels; and different color channels than the reduced set of color channels (e.g., FIG. 1, the CNN includes an input layer 101, a hidden layer 102, and an output layer 103. The input layer 101 has 4 inputs; the hidden layer 102 has 3 outputs; the output layer 103 has 2 outputs; and the CNN finally outputs 2 images, paragraph 32).
Regarding claim 3, Liu discloses wherein the processor is configured to combine the sub-network and the additional sub-network to create an ensemble network (e.g., FIG. 1 is a schematic diagram of a CNN. For instance, the CNN can be used for image processing, which uses images as input and output, and replaces scalar weights by convolution kernels. FIG. 1 only shows a CNN having a 3-layered structure, and the embodiments of the present disclosure are not limited to this case. As shown in FIG. 1, the CNN includes an input layer 101, a hidden layer 102, and an output layer 103. The input layer 101 has 4 inputs; the hidden layer 102 has 3 outputs; the output layer 103 has 2 outputs; and the CNN finally outputs 2 images, paragraph 32, figure 1).
Regarding claim 4, Liu discloses wherein the processor is configured to select the sub-network and/or the additional sub-network for processing instances of input image data based at least in part on one or more color channels to be processed (e.g., FIG. 1, the CNN further includes a first activation layer 203 and a second activation layer 204. The first activation layer 203 is disposed after the first convolution layer 201, and the second activation layer 204 is disposed after the second convolution layer 202, paragraph 35).
Regarding claim 5, Liu discloses wherein the processor is configured to provide representations of the sub-network and the additional sub-network to an additional processor, the representations of the sub-network and the additional sub-network configured to be combined by the additional processor into an ensemble network to be used for processing instances of input image data (e.g., the processor 520 can control other components in the image processing device to realize desired functions. The processor 520 can be an element having data processing capability and/or program execution capability, such as a central processing unit (CPU), a tensor processing unit (TPU), or a graphics processing unit (GPU). The CPU can have an X86 or ARM architecture, etc. The GPU can be integrated directly on the motherboard alone or built into the Northbridge chip of the motherboard. The GPU can also be built into the CPU, paragraph 219).
Regarding claim 6, Liu discloses wherein the processor is configured to provide a representation of the sub-network to an additional processor, the representation of the sub-network configured to be used by the additional processor for processing instances of input image data(e.g., the processor 520 can control other components in the image processing device to realize desired functions. The processor 520 can be an element having data processing capability and/or program execution capability, such as a central processing unit (CPU), a tensor processing unit (TPU), or a graphics processing unit (GPU). The CPU can have an X86 or ARM architecture, etc. The GPU can be integrated directly on the motherboard alone or built into the Northbridge chip of the motherboard. The GPU can also be built into the CPU, paragraph 219)
Regarding claim 7, Liu discloses wherein generating the sub-network includes creating a copy of the neural network from which internal elements for processing at least one color channel are removed (e.g., the input layer 101 with 4 inputs, sub-network 102 with 3 inputs, figure 1).
Regarding claim 8, claim 8 is a method claim with limitations similar of limitations of claim 1. Therefore, claim 8 is rejected as set forth above as claim 1.
Regarding claim 9, claim 9 is a method claim with limitations similar of limitations of claim 2. Therefore, claim 9 is rejected as set forth above as claim 2.
Regarding claim 10, claim 10 is a method claim with limitations similar of limitations of claim 3. Therefore, claim 10 is rejected as set forth above as claim 3.
Regarding claim 11, claim 11 is a method claim with limitations similar of limitations of claim 4. Therefore, claim 11 is rejected as set forth above as claim 4.
Regarding claim 12, claim 12 is a method claim with limitations similar of limitations of claim 5. Therefore, claim 12 is rejected as set forth above as claim 5.
Regarding claim 13, claim 13 is a method claim with limitations similar of limitations of claim 6. Therefore, claim 13 is rejected as set forth above as claim 6.
Regarding claim 14, claim 14 is a method claim with limitations similar of limitations of claim 7. Therefore, claim 14 is rejected as set forth above as claim 7.
Regarding claim 15, claim 15 is a processor claim with limitations similar of limitations of claim 1. Therefore, claim 15 is rejected as set forth above as claim 1.
Regarding claim 16, claim 16 is a processor claim with limitations similar of limitations of claim 2. Therefore, claim 16 is rejected as set forth above as claim 2.
Regarding claim 17, claim 17 is a processor claim with limitations similar of limitations of claim 3. Therefore, claim 17 is rejected as set forth above as claim 3.
Regarding claim 18, claim 18 is a processor claim with limitations similar of limitations of claim 4. Therefore, claim 18 is rejected as set forth above as claim 4.
Regarding claim 19, claim 19 is a processor claim with limitations similar of limitations of claim 5. Therefore, claim 19 is rejected as set forth above as claim 5.
Regarding claim 20, claim 20 is a processor claim with limitations similar of limitations of claim 6. Therefore, claim 20 is rejected as set forth above as claim 6
.Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUANG N VO whose telephone number is (571)270-1121. The examiner can normally be reached Monday-Friday, 7AM-4PM, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Abderrahim Merouan can be reached at 571-270-5254. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/QUANG N VO/ Primary Examiner, Art Unit 2683
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