DETAILED ACTION
The instant action is in response to application 23 August 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Response to Arguments
The 112(b) rejection has been withdrawn.
Applicants remarks on the merits have been considered but are moot for not considering the present references.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
For method claims, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated. (The claims have been condensed.)
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 12 are rejected under 35 U.S.C. 103 as being unpatentable over De Rooji (US 20150049528) in view of Yang (US 7116090)
As to claim 1, De Rooij discloses (see image below) a power supply apparatus, comprising: a power factor correction (PFC) circuit; and a control circuit configured to control an operation of the PFC circuit, wherein the PFC circuit comprises:a power inputter configured to receive alternating current (AC) voltage to be rectified; an inductor having a first end coupled to a first end of the power inputter; a first switching element configured to be turned on and turned off, according to a first control signal, and having a first end coupled to a second end of the inductor; a second switching element configured to be turned on and turned off, according to a second control signal, and having a first end commonly coupled to the second end of the inductor and the first end of the first switching element; and an outputter configured to output a direct current (DC) voltage through an output capacitor, and having a first end coupled to a second end of the second switching element and a second end coupled to a second end of the first switching element, wherein the control circuit is further configured to: apply the first control signal to the first switching element and the second control signal to the second switching element such that the first switching element and the second switching element are alternately turned on, and turn off.
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Though feedback and deadtime in order to prevent shoot through is heavily implied to not short the load, De Rooji does not explicitly disclose based on a sensing voltage being less than a control voltage, and a predetermined time being elapsed from a time point when the first switching element is turned on.
Yang teaches A power supply apparatus, comprising: a power factor correction (PFC) circuit (title, PFC circuit); and a control circui (Fig. 7, item 100)t configured to control an operation of the PFC circuit, wherein the PFC circuit comprises: a power inputter (Fig. 1, item 40) configured to receive alternating current (AC) voltage to be rectified ;an inductor having a first end coupled to a first end of the power inputter (Fig. 7, item 25); a first switching element configured to be turned on and turned off (Fig. 7, item 10), according to a first control signal (Vg), and having a first end coupled to a second end of the inductor; a second switching element configured (20) to be turned on and turned off, and having a first end commonly coupled to the second end of the inductor and the first end of the first switching element; and an outputter configured to output a direct current (DC) voltage through an output capacitor (Fig. 7, item 50), and having a first end coupled to a second end of the second switching element and a second end coupled to a second end of the first switching element, wherein the control circuit is further configured to:apply the first control signal to the first switching element such that the first switching element and the second switching element are alternatelturned on, and turn off the first switching element through the first control signal based on a sensing voltage being less than a control voltage (Fig. 8, item 120) and a predetermined time being elapsed from a time point when the first switching element is turned on (abstract “The program terminal determines the slew rate of the ramp signal and the maximum on-time of the switching signal.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use maximum on time to limit the frequency.
As to claim 12, this is a method claim corresponding to the apparatus claim above (which has more limitations) and is obvious for similar reasons.
Claims 2-3, 5, 6 13, 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over De Rooji (US 20150049528) in view of Yang (US 7116090) and Chen (US 20140340949).
As to claim 2, De Rooji in view of Yang does not disclose wherein: the PFC circuit further comprises a sensing resistor having a first end coupled to the second end of the first switching element and second end coupled to a second end of the power inputter, and the control circuit is further configured to, based on the sensing voltage applied to the second end of the sensing resistor reaching the control voltage and the predetermined time being elapsed, turn off the first switching element through the first control signal, the control voltage having been determined based on the DC voltage output through the outputter.
Chen teaches wherein: the PFC circuit further comprises a sensing resistor having a first end coupled to the second end of the first switching element and second end coupled to a second end of the power inputter, and the control circuit is further configured to, based on the sensing voltage applied to the second end of the sensing resistor reaching the control voltage and the predetermined time being elapsed, turn off the first switching element through the first control signal, the control voltage having been determined based on the DC voltage output through the outputter. (PWM comparator 33 does this by comparing the sensed current to the error generated ramp).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use the control system of Kim to reduce phase delay (¶8).
As to claim 3, De Rooij in view of Yang and Chen teaches wherein the control circuit comprises: an error amplifier (322) configured to amplify and output a difference between a voltage distribution value of the DC voltage and a first reference voltage; and a first comparator (33) configured to compare the control voltage and the sensing voltage, the control voltage being a reverse of an output of the error amplifier, wherein the control circuit is further configured to determine whether the sensing voltage reaches the control voltage based on an output of the first comparator. As to the limitation, the control voltage being a reverse of an output of the error amplifier, this is design choice. Inverting would allow one of ordinary skill to quickly and cheaply increase the magnitude of a control system, whereas leaving the signal as is would reduce parts count. The advantages and disadvantages of both are well known and therefore this is obvious design choice.
As to claim 5, De Rooji in view of Yang and Chen teaches wherein the control circuit comprises: a sawtooth generator configured to generate a sawtooth wave in which a voltage rises at a predetermined slope from a time when the first switching element is turned on (Chen 313); and a second comparator (Chen 33) configured to compare the sawtooth wave output from the sawtooth generator with a second reference voltage (output 323), wherein the control circuit is further configured to generate, based on an output of the second comparator, the 'first control signal for turning off the 'first switching element (a pwm signal turns the first switch off and on).
As to claim 6, De Rooji in view of Yang and Chin teaches wherein the predetermined time is preset to a maximum time interval on which the first switching element is turned on at a minimum voltage of the AC voltage (Fig. 6 De Rooji).
As to claims 13, 15, 16, 17, these are method claim corresponding to the apparatus claim above and are obvious for similar reasons.
Claims 7-8, 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over De Rooji (US 20150049528) in view of Yang (US 7116090) and Duduman (US 20180331682).
As to claim 7, Though strongly implied in a boost converter to prevent unintentionally shorting the load, De Rooj in view of Yang i does not explicitly disclose wherein the control circuit is 'further configured to: turn on the second switching element through the second control signal after a first deadtime from a first time point when the first switching element is turned off; and turn on the first switching element through the first control signal after a second deadtime from a second time point when the second switching element is turned off.
Duduman teaches wherein the controlcircuit is 'further configured to:turn on the second switching element through the second control signal after a first deadtime from a first time point when the first switching element is turned off; and turn on the first switching element through the first control signal after a second deadtime from a second time point when the second switching element is turned off (Duduman, Fig. 7B)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use controllable deadtime as disclosed in Duduman to prevent shorting the load.
As to claim 8, De Rooji in view of Duduman teaches wherein a 'first duration of the 'first deadtime is different from a second duration of the second deadtime (Fig. 7B).
As to claims 18-19, these are method claim corresponding to the apparatus claim above and is obvious for similar reasons.
Claims 20 is rejected under 35 U.S.C. 103 as being unpatentable over De Rooji (US 20150049528) in view of Duduman (US 20180331682), Yang (US 7116090) ) and Chen (US 20140340949).
As to claim 20, De Rooji discloses A power supply apparatus, comprising: a power factor correction (PFC) circuit; and acontrol circuit configured to control an operation of the PFC circuit, wherein the PFC circuit comprises :a power inputter configured to receive alternating current (AC) voltage to be rectified; an inductor having a first end coupled to a first end of the power inputter; a first switching element configured to be turned on and turned off, according to a first control signal, and having a first end coupled to a second end of the inductor;a second switching element configured to be turned on and turned off, according to a second control signal, and having a first end commonly coupled to the second end of the inductor and the first end of the first switching element; and an outputter configured to output a direct current (DC) voltage through an output capacitor, and having a first end coupled to a second end of the second switching element and a second end coupled to a second end of the first switching element, wherein the control circuit is further configured to:apply the first control signal to the first switching element and the second control signal to the second switching element such that the first switching element and the second switching element are alternately turned on turned off; and turn off the first switching element through the first control signal (see image above and rejection of claim 1).
He does not explicitly teach urn on the first switching element through the first control signal after a second deadtime from a second time point when the second switching element isturned off; and turn off the first switching element through the first control signal based on a sensing voltage being less than a control voltage and a predetermined time being elapsed from a time point when the first switching element is turned on.
Duduman teaches turn on the second switching element through the second control signal after a first deadtime from a first time point when the first switching element is turned off; and turn on the first switching element through the first control signal after a second deadtime from a second time point when the second switching element is turned off (Fig. 7B, which shows different dead times for the HS and LS switches).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use controllable deadtime as disclosed in Duduman to prevent shorting the load.
Yang teaches and turn off the first switching element through the first control signal based on a sensing voltage being less than a control voltage and a predetermined time being elapsed from a time point when the first switching element is turned on (see claim 1 above).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use maximum on time to limit the frequency.
Claims 9, 11 are rejected under 35 U.S.C. 103 as being unpatentable over De Rooji (US 20150049528) in view of Yang (7116090), Duduman (US 20180331682) and Chiu (US 20200259415).
As to claim 9, De Reooji in view of Yang and Duduman does not teach wherein the control circuit is further configured to turn off the second switching element through the second control signal after a predetermined delay time from a third time point when a current of the inductor becomes zero.
Chiu teaches wherein the control circuit is further configured to: turn off the second switching element through the second control signal after a predetermined delay time from a third time point when a current of the inductor becomes zero (Fig. 1, item 10, 21, 30)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use a dynamic delay in the ZCD in order to adjust to shifting conditions (¶2).
As to claim 11, De Reooji in view of Duduman and Chiu teaches wherein the control circuit further comprises a digital circuit configured to generate the first deadtime, the second deadtime, and a preset delay time (Chiu and Duduman both teach digital logic).
Claims 21 is rejected under 35 U.S.C. 103 as being unpatentable over De Rooji (US 20150049528) in view of Duduman (US 20180331682) and Yang (US 7116090).
As to claim 21, De Rooji in view of Duduman and Yang does not disclose wherein: the PFC circuit further comprises a sensing resistor having a first end coupled to the second end of the first switching element and second end coupled to a second end of the power inputter, and the control circuit is further configured to, based on the sensing voltage applied to the second end of the sensing resistor reaching the control voltage and the predetermined time being elapsed, turn off the first switching element through the first control signal, the control voltage having been determined based on the DC voltage output through the outputter.
Chen teaches wherein: the PFC circuit further comprises a sensing resistor having a first end coupled to the second end of the first switching element and second end coupled to a second end of the power inputter, and the control circuit is further configured to, based on the sensing voltage applied to the second end of the sensing resistor reaching the control voltage and the predetermined time being elapsed, turn off the first switching element through the first control signal, the control voltage having been determined based on the DC voltage output through the outputter. (PWM comparator 33 does this by comparing the sensed current to the error generated ramp).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use the control system of Kim to reduce phase delay (¶8).
Claims 10 is rejected under 35 U.S.C. 103 as being unpatentable over De Rooji (US 20150049528) in view of Yang (7116090), Duduman (US 20180331682) Chiu (US 20200259415) and Chen (US 20140340949).
As to claim 11, De Reooji in view of Duduman and Chi teaches the control circuit comprises a third comparator configured to compare a sensing voltage applied to the second end of the sensing resistor with a critical voltage, and the control circuit is further configured to determine the third time point at which the current of the inductor becomes zero based on an output of the third comparator (Chiu, Fig. 1).
Though they do teach a method of sensing zero current, they do not explicitly teach wherein: the PFC circuit further comprises a sensing resistor having a first end coupled to the second end of the first switching element and a second end coupled to a second end of the power inputter.
Chen teaches wherein: the PFC circuit further comprises a sensing resistor (312) having a first end coupled to the second end of the first switching element and a second end coupled to a second end of the power inputter.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use sensing resistor in order to increase stability of the system.
Conclusion
Examiner has cited particular column, paragraph, and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Applicant's submission of an information disclosure statement under 37 CFR 1.97(c) with the timing fee set forth in 37 CFR 1.17(p) on 15 December 2025 prompted the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 609.04(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M NOVAK whose telephone number is (571)270-1375. The examiner can normally be reached on 9AM-5PM,Monday through Thursday, EST.
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/PETER M NOVAK/ Primary Examiner, Art Unit 2839