DETAILED ACTION
This action is responsive to U.S. Patent Application No. 18/237,271 filed on 23 August 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of Applicant' s Information Disclosure Statement(s) (IDS). The IDS(es) has/have been considered.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Applicant’s election without traverse of the Species 1 embodiment in the reply filed on 17 December 2025 is acknowledged.
Accordingly, claims 3, 10, and 11 are withdrawn from further consideration, as they are drawn to one or more nonelected embodiments.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 2, 4, 6, 7, and 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
“The essential inquiry pertaining to this requirement is whether the claims set out and circumscribe a particular subject matter with a reasonable degree of clarity and particularity. ‘As the statutory language of “particular[ity]” and “distinct[ness]” indicates, claims are required to be cast in clear—as opposed to ambiguous, vague, indefinite—terms. It is the claims that notify the public of what is within the protections of the patent, and what is not.’” MPEP § 2173.02(II) (quoting In re Packard, 751 F.3d 1307, 1313, 110 USPQ2d 1785, 1788 (Fed. Cir. 2014)).
Regarding claim 1: claim 1 states, in relevant part: “and a capacitor arranged on the substrate and connected at one end to at least either the circuit or the analog circuit via a connection wire.” The quoted limitation uses the phrase “at least,” as well as “either,” which appear to directly contradict one other, thus rendering the scope of the claim unclear. In particular, “at least” encompasses one or more (i.e., both) of the circuit and/or the analog circuit, while “either” encompasses one of the circuit or the analog circuit, but not both (i.e., only one of). Accordingly, it is unclear whether the abovementioned portion of claim 1 encompasses (1) a connection between the capacitor and one or more of the circuit and/or the analog circuit, or (2) a connection between the capacitor and only one of the circuit and/or the analog circuit. For the purposes of examination, the abovementioned limitation has been interpreted in accordance with interpretation (1).
Claims 2 and 4-9, which depend from claim 1, are also rejected under § 112(b) for at least the same reason as claim 1.
Regarding claim 2: Claim 2 states, in relevant part: “wherein series resonance of an inductance of the connection wire and a capacitance of the capacitor is based on the clock frequency.” This limitation renders the scope of the claim unclear because it is unclear whether the limitation encompasses, e.g., (1) any relationship between inductance and capacitance and any clock frequency of the circuit, (2) that specific relationship between inductance and capacitance and the clock frequency of the circuit (i.e., setting f equal to fclk as disclosed in [0018] of the instant disclosure), or (3) some other relationship between inductance and capacitance and a clock frequency of the circuit (i.e., frequency of a higher harmonic fclk*n as disclosed in [0018] of the instant disclosure).
Claims 4-6, which depend from claim 2, are also rejected under § 112(b) for at least the same reason as claim 2.
Regarding claim 4: Claim 4 recites the limitation "the other end." There is insufficient antecedent basis for this limitation in the claim.
Regarding claim 6: Claim 6 recites, in relevant part: “wherein the circuit is at least either a digital circuit or a power supply circuit . . . .” The quoted limitation uses the phrase “at least,” as well as “either,” which appear to directly contradict one other, thus rendering the scope of the claim unclear. In particular, “at least” encompasses one or more (i.e., both) of a digital circuit and/or a power supply circuit, while “either” encompasses one of a digital circuit or a power supply circuit, but not both (i.e., only one of). Accordingly, it is unclear whether the abovementioned portion of claim 1 encompasses (1) a connection between the capacitor and one or more of the circuit and/or the analog circuit, or (2) a connection between the capacitor and only one of the circuit and/or the analog circuit. For the purposes of examination, the abovementioned limitation has been interpreted in accordance with interpretation (1).
Claim 6 further recites the limitation “the other end.” There is insufficient antecedent basis for this limitation in the claim.
Regarding claim 7: Claim 7 recites the limitation “the other end.” There is insufficient antecedent basis for this limitation in the claim.
Claims 8-9, which depend from claim 7, are also rejected under § 112(b) for at least the same reason as claim 7.
Regarding claim 8: Claim 7 recites the limitation “the other end.” There is insufficient antecedent basis for this limitation in the claim.
Claim 9, which depends from claim 8, are also rejected under § 112(b) for at least the same reason as claim 8.
Applicant may cancel the claims, amend the claims, or present a sufficient showing that the claims comply with the statutory requirements.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, and 4-6 are rejected under 35 U.S.C. § 102(a)(2) as being anticipated by U.S. Patent No. 9,960,756 (filed Dec. 2, 2016) (hereinafter “Harwalkar”).
Regarding independent claim 1, Harwalkar discloses: A semiconductor device () comprising:
a substrate (FIG. 3, depicting a block diagram of an electronic system including a an IC chip 20 mounted on a PCB, Col. 6, Lines 10-15) including at least a grounding terminal (FIG. 3, e.g., PCB ground conductor 60, Col. 8, Lines 25-45) and being at a same potential as the grounding terminal (FIG. 3, depicting wherein the PCB is at a same potential as the ground pad PCB ground conductor 60);
a semiconductor chip arranged on the substrate (FIG. 3, IC chip 20 on the PCB), connected to the grounding terminal via a first bonding wire (FIG. 3, depicting wherein the IC chip 20 is connected to the PCB ground conductor 60 by a bond wire (i.e., a finite impedance), Col. 8, Lines 25-45), and including a circuit driven with a predetermined clock frequency (FIGS. 3/4, voltage regulator 28, Col. 7, Lines 45-65) and an analog circuit (FIGS. 3/4, e.g., high impedance circuit 12 which may be an inductor LH, Col. 12, Lines 1-5); and
a capacitor arranged on the substrate (FIGS. 3/5, e.g., capacitor CL1 arranged on the PCB, Col. 11, Lines 10-25) and connected at one end to at least either the circuit or the analog circuit via a connection wire (FIGS. 3/5, depicting wherein the capacitor CL1 is electrically connected by bypass path 42 to the high impedance circuit 12 at one end).
Regarding claim 2, Harwalkar further discloses wherein series resonance of an inductance of the connection wire and a capacitance of the capacitor is based on the clock frequency (FIGS. 3/4/5, Col. 10-11: “In the first and second embodiments, the capacitance of the first and second capacitors (CL1 and CL2) is selected to present a relatively low impedance to the noise current at the operating frequency range of the noise sensitive circuit 22. As known in the art, capacitive reactance (i.e., the imaginary part of impedance) is inversely proportional to both capacitance and frequency, according to the equation below. . . . In EQ. 3, Xc is the capacitive reactance, C is the capacitance and f is the frequency of operation of the noise sensitive circuit. When noise sensitive circuit 22 is configured for operation in a GHz frequency range (e.g., about 2.4 GHz to about 2.6 GHz), the first and second capacitors (CL1 and CL2) may be implemented with 1 pF to 1 nF capacitors to present a relatively low impedance of about 1-10Ω to the noise current. Selecting the capacitance based on the operating frequency of the noise sensitive circuit enables noise current frequencies similar to the operating frequency of the noise sensitive circuit to be routed around the noise sensitive circuit via the first and second bypass paths 42, 44.”).
Regarding claim 4, Harwalkar further discloses wherein the connection wire is connected to an input side wire of the analog circuit at one end and to the one end of the capacitor at the other end (FIG. 3/4/5, depicting wherein the bypass path 42 is connected at one end to a node before the high impedance circuit 12 and to one end of the capacitor CL1 at another end).
Regarding claim 5, Harwalkar further discloses wherein the semiconductor chip further includes a second wire connected to the grounding terminal via the first bonding wire (FIGS. 3/4/5, depicting various connection points/wires between the PCB ground conductor 60 and the bond wire after, e.g., ground pad GND3, including, e.g., bypass path 44 electrically connected to the PCB ground conductor 60), and the semiconductor device further comprises a third wire connecting the substrate and the second wire to each other (IGS. 3/4/5, depicting, e.g., the bond wire after ground pad GND3, which would electrically connect the PCB and the bypass path 44).
Regarding claim 6, Harwalkar further discloses wherein the circuit is at least either a digital circuit or a power supply circuit (FIGS. 3/4/5, the circuit is a voltage regulator 28), and the analog circuit is connected to the circuit at one end and to the second wire at the other end (FIGS. 3/4/5, depicting wherein the high impedance circuit 12 is connected to the voltage regulator 28 at one end and to the bypass path 44 at the other end).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-9 are rejected under 35 U.S.C. § 103 as being unpatentable over Harwalkar in view of U.S. Patent Publication No. 2016/0020041 (filed June 5, 2015) (hereinafter “Ahn”).
Regarding claim 7, Harwalkar does not specifically disclose wherein the capacitor is a multilayer ceramic chip capacitor connected to the substrate at the other end.
In the same field of endeavor, Ahn discloses a capacitor device (FIG. 13, electronic component 100, [0181]) including a multilayer ceramic chip capacitor (FIG. 13, MLCC 110, [0053]). Regarding the MLCC, in [0192]-[0193], Ahn states: “According to exemplary embodiments of the present disclosure, a composite electronic component having an excellent acoustic noise reduction effect may be provided. Also, according to exemplary embodiments of the present disclosure, a composite electronic component having high capacity, low ESR/ESL, enhanced DC-bias characteristics, and a small chip thickness may be provided.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed semiconductor device of Harwalkar by substituting capacitor device of Ahn in order to improve noise reduction, reduce chip thickness, increase capacity, and provide reduced ESR/ESL. See Ahn [0192]-[0193].
Moreover, substitution of the capacitor device of Ahn would result in a configuration wherein the capacitor device is connected to the substrate at the other end (FIGS. 3/4/5, depicting wherein the capacitor device 100 of Ahn would be connected to the PCB ground conductor 60 at one end).
Regarding claim 8, Harwalkar in view of Ahn further discloses wherein the capacitor is connected to the substrate at the other end via a conductive material (FIGS. 3/4/5, depicting wherein a bond wire (i.e., a finite impedance) connects the capacitor CL1, corresponding to the capacitor device 100 of Ahn, to the PCB ground conductor 60).
Regarding claim 9, Harwalkar in view of Ahn further discloses wherein the one end of the capacitor, connected to the connection wire, is arranged on the substrate via an insulator (FIG. 13, depicting wherein the capacitor device 100 of Ahn further includes an insulating sheet 140 disposed between the MLCC and the PCB of Ahn, which would be disposed between the MLCC and the PCB of Harwalkar).
Conclusion
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/ADAM D WEILAND/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813