DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim 1 and 20 have been considered but are moot in view of the new ground of rejection necessitated by amendment. The drawing objection with respect to the feature, “wherein at least one of the first air gaps and one of the second air gaps is interconnected,” of claim 5 is maintained. Applicant argues that the first air gap 4111 and the second air gap 4113 are explicitly shown as interconnected in FIG. 4A. Examiner respectfully disagrees. FIG. 4A merely shows that the first air gap 4111 and the second air gap 4113 are overlapping in a Z-direction projection, in a similar manner as bit line 4031 is shown overlapping the second air gap 4113 in FIG. 4A. The prior drawing rejection with respect to the feature, “first contact layers, wherein each of the first contact layers is between a corresponding word line and a corresponding the gate structure,” of claim 9 is withdrawn in view of the amendment to claim 9. The prior §112 rejections are withdrawn in view of the amended claims.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, “wherein at least one of the first air gaps and one of the second air gaps is interconnected,” of claim 5 and, “wherein each of the word lines is connected to a gate structure of the vertical transistor,” of claim 2 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-7, 9-12, 14, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Hua et al. (CN 114530420 A; hereinafter referred to as “Hua”) in view of Shih (US PGPub 20210175236 A1; hereinafter referred to as "Shih”).
Re claim 1: Hua teaches a memory device comprising: an array of memory cells (para. n0033-n0034; para. 218), wherein each of the memory cells comprises a vertical transistor (para. n0033, n0061-n0062; para. 218; FIG. 34a, 3a: el. 10 | memory cell comprising a transistor of the transistor pair 10, as labeled in FIG. 3a, and a connected capacitor 116), wherein the vertical transistor comprises a semiconductor body extending in a first direction (para. n0130; FIG. 34a: el. (101, 103, 104)|semiconductor body (101, 103, 104) of the vertical transistor extends in a first direction perpendicular to the plane of the substrate); bit lines coupled to the memory cells, wherein each of the bit lines is connected to a first end of the semiconductor body (para. 223; FIG. 34a: el. 110, 103); first air gaps, wherein at least one of the first air gaps is between adjacent bit lines (Fig. 34b: el. 115, 110; para. 224); second air gaps, wherein at least one of the second air gaps is between adjacent semiconductor bodies of adjacent memory cells (FIG. 34a: el. 114; para. 0219| second air gaps such as second air gap 114 between adjacent vertical transistor semiconductor bodies of adjacent memory cells); word lines coupled to the memory cells (para. n0034; FIG. 1); gate line structures coupled to the memory cells (FIG. 34a: el. 118, annotated FIG. 34a: el. gate line structure| annotated FIG. 34a provided below); and gate line structure dielectric layers, wherein each two adjacent gate line structures are in direct contact with a corresponding gate line structure dielectric layer (annotated FIG. 34a: el. gate line structure, line structure dielectric layer| annotated FIG. 34a provided below). Hua discloses that the word line is connected to a gate region of the transistor structure, but fails to directly disclose how the word lines are integrated to the gate region of the transistor, and thus fails to directly disclose word line dielectric layers, wherein each two adjacent word lines are in direct contact with a corresponding word line dielectric layer.
In a similar field of endeavor, Shih teaches a memory semiconductor device comprising pairs of vertical transistors and adjacent capacitors (para. abstract, 32, 52, 62: FIG. 3, 4), wherein conductive word lines (FIG. 1, 39-40: el. 601) extend adjacent to and alongside channel regions (FIG. 39-40: el. 405) of the vertical transistors, and a gate region adjacent to the channel region of the vertical transistor is occupied by a portion of the continuous word line (FIG. 1, 38-40; para. 35, 58-61, 85-86). Shih teaches gate line structures formed as the integrated portions of the word line which are adjacent to the channel region of a vertical transistor. Shih further teaches forming continuous word lines in the same plane as the channel structure as a simple processing method, which has a limited number of deposition and etching steps, for forming a pair of word lines adjacently coupled to channel regions of vertical transistors (para. 109-111, 2). The combination of Hua and Shih teaches that the gate line structure of Hua can be a portion of a continuous word line formed by a simple processing method. The combination of Hua and Shih teaches word lines coupled to the memory cells (Hua - para. n0034); and word line dielectric layers (Hua – annotated FIG. 34a: el. line structure dielectric layer| annotated FIG. 34a provided below), wherein each two adjacent word lines are in direct contact with a corresponding word line dielectric layer (Hua – annotated FIG. 34a: el. line structure dielectric layer, line 1, line 2| annotated FIG. 34a provided below).
It would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Hua and Shih, to enable using the continuous word line adjacent to a channel region of Shih in the memory device of Hua, for the benefit of simplifying a manufacturing process by utilizing a known method for efficiently integrating a word line into a vertical transistor semiconductor device.
PNG
media_image1.png
827
1145
media_image1.png
Greyscale
Re claim 2: The combination of Hua and Shih teaches the memory device of claim 1, wherein each of the word lines is connected to a gate structure of the vertical transistor (Hua – n0034, n0057| Hua teaches word lines connected to gate of the transistor, and the combination of Hua and Shih teaches continuous word lines connected to and continuous with the gate line structure of FIG. 34a, which is further connected to the gate oxide 117 of the transistor), wherein the gate structure is in contact with a first side of the semiconductor body (Hua – annotated FIG. 34a: el. 117, semiconductor body of vertical transistor| annotated FIG. 34a provided in Re claim 1 section).
Re claim 3: The combination of Hua and Shih teaches the memory device of claim 1, wherein: each of the first air gaps extends in a second direction (Hua - para. 224|first air gaps 115 extend in a second direction which lies within the plane of the substrate); each of the bit lines extends in the second direction (Hua - para. 223); each of the second air gaps extends in a third direction (Hua - para. 219, 218, n0054|second air gaps 114 extend in a third direction which lies in the plane of the substate and is perpendicular to the second direction); and each of the word lines extends in the third direction (Hua - FIG. 1|word lines extend along the device in a third direction orthogonal to bit lines), and wherein the first direction is perpendicular to the second direction, and the second direction is perpendicular to the third direction (Hua - para. 218, n0054; FIG. 34d).
Re claim 4: The combination of Hua and Shih teaches the memory device of claim 3, wherein at least one of the first air gaps extends to the semiconductor body in the first direction (Hua - FIG. 34b; first air gaps extend to the semiconductor body encompassing the first electrode 103, semiconductor body 101, and second electrode 104 (Hua - supporting FIG. 14, 16, 34a; supporting para. n0093).
Re claim 5: The combination of Hua and Shih teaches the memory device of claim 1, wherein at least one of the first air gaps and one of the second air gaps is interconnected (Hua - para. 224; FIG. 34c).
Re claim 6: The combination of Hua and Shih teaches the memory device of claim 1, wherein each of the memory cells further comprises: a storage structure coupled to a second end of the semiconductor body (Hua - FIG. 34a: el. 116; para. 228).
Re claim 7: The combination of Hua and Shih teaches the memory device of claim 6, further comprising: a substrate coupled to the storage structure remote from the vertical transistor (Hua - FIG. 34a: el. 10-2, 116; para. n0125).
Re claim 9: The combination of Hua and Shih teaches the memory device of claim 6, further comprising: first contact layers, wherein each of the first contact layers is between a corresponding storage structure and a corresponding semiconductor body (Hua – para. n0087| storage structure formed of capacitor 116 and capacitor 116 is connected to semiconductor body (104, 101, 103) by means of a metallic memory cell contact layer).
Re claim 10: The combination of Hua and Shih teaches the memory device of claim 1, further comprising: second contact layers (Hua - FIG. 34a-b: el. 122, as labelled in FIG. 23; para. n0107), wherein each of the second contact layers is between a corresponding bit line and a corresponding semiconductor body (Hua - FIG. 34a-b|contact layer 122 (as labelled in FIG. 23) is between bit line 110 and the semiconductor body encompassing elements 101, 103, 104 in FIG. 34a).
Re claim 11: The combination of Hua and Shih teaches the memory device of claim 1, further comprising: a first dielectric layer, wherein at least a portion of the first dielectric layer encapsulates at least one of a corresponding first air gap or a corresponding second air gap (Hua - FIG. 34a: el. 106; para. n0124).
Re claim 12: The combination of Hua and Shih teaches the memory device of claim 1, further comprising: a first dielectric layer, wherein at least a portion of the first dielectric layer is between two adjacent semiconductor bodies of adjacent memory cells (Hua - FIG. 34a: el. 106 | dielectric layer 106 is between semiconductor body 1002 to the left and an adjacent semiconductor body to the right of both layer 106 and air gap 114).
Re claim 14: The combination of Hua and Shih teaches the memory device of claim 11, wherein the first dielectric layer (Hua - FIG. 34a: el. 106) and the word line dielectric layers (Hua – annotated FIG. 34a: el. line structure dielectric layer| annotated FIG. 34a provided in Re claim 1 section) comprise different materials (Hua - para. n083, n0068|dielectric layer 106 is made up of silicon dioxide and the word line dielectric layer is made up of dielectric 121 encapsulated in dielectric; dielectric 121 is made up of silicon nitride, and thus the first dielectric layer and the word line dielectric layer comprise different materials).
Re claim 21: The combination of Hua and Shih teaches the memory device of claim 3, further comprising: second contact layers (Hua - FIG. 34a-b: el. 122, as labelled in FIG. 22 and 23; para. n0107), wherein each of the second contact layers is between a corresponding bit line and a corresponding semiconductor body (Hua - FIG. 34a-b|contact layer 122 (as labelled in FIG. 22 and 23) is between bit line 110 and the semiconductor body encompassing elements 101, 103, 104 in FIG. 34a), and each of the second contact layers extends along with each of the bit lines in the second direction (Hua - FIG. 34a, 22: el. 122, 110| second contact layers 122 extend in the second direction (y-direction), bit lines 110 extend in the second direction (y-direction), second contact layers 122 are connected to bit lines 110 and thus extend along with the bit lines 110 in the second direction).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Hua in view of Shih as applied to claim 1 above, and further in view of Cho et al. (US 8906775 B2; hereinafter referred to as “Cho”).
Re claim 8: The combination of Hua and Shih teaches the memory device of claim 1, wherein the semiconductor body comprises a semiconductor material (Hua - para. n0050|semiconductor body formed from material of wafer 10-1 which is a semiconductor wafer such as a silicon wafer). Hua is silent as to the crystallinity of the semiconductor wafer and thus of the semiconductor body.
In a similar field of endeavor, Cho teaches forming a vertical transistor body from the material of a single crystal semiconductor substrate to be used as a semiconductor device such as DRAM (col. 3: line 47-col. 4: line 11; col. 6: line 25-27). Cho teaches a semiconductor body of a vertical transistor comprising a single crystalline semiconductor material (col. 3: line 47-col. 4: line 11).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of the combination of Hua and Shih with the teachings of Cho, to enable using the single crystalline semiconductor transistor body of Cho in the vertical transistor of the memory device of the combination of Hua and Shih, for the benefit of improving device performance by reducing resistance and carrier scattering in the semiconductor body channel.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Hua in view of Shih and Kim (US PGPub 20160104798 A1; hereinafter referred to as “Kim”).
Re claim 20: Hua teaches a memory system comprising: a memory device (para. n0031), wherein the memory device comprises: an array of memory cells (para. n0033-n0034; para. 218| memory device comprises array of transistor units connected to capacitor units which forms an array of memory cells), wherein each of the memory cells comprises a vertical transistor (para. n0061-n0062; para. 218; FIG. 34a: el. 10), wherein the vertical transistor comprises a semiconductor body extending in a first direction (para. n0130; FIG. 34a: el. 101, 103, 104); bit lines coupled to the memory cells, wherein each of the bit lines is connected to a first end of the semiconductor body (para. 223); first air gaps, wherein at least one of the first air gaps is between adjacent bit lines (Fig. 34b: el. 115, 110; para. 224); second air gaps, wherein at least one of the second air gaps is between adjacent semiconductor bodies of adjacent memory cells (FIG. 34a: el. 114; para. 0219); word lines coupled to the memory cells (para. n0034; FIG. 1). Hua discloses that the word line is connected to a gate region of the transistor structure, but fails to directly disclose how the word lines are integrated to the gate region of the transistor, and thus fails to directly disclose word line dielectric layers, wherein each two adjacent word lines are in direct contact with a corresponding word line dielectric layer. Furthermore, Hua fails to teach a memory system comprising: a memory controller coupled to the memory device.
In a similar field of endeavor, Shih teaches a memory semiconductor device comprising pairs of vertical transistors and adjacent capacitors (para. abstract, 32, 52, 62: FIG. 3, 4), wherein conductive word lines (FIG. 1, 39-40: el. 601) extend adjacent to and alongside channel regions (FIG. 39-40: el. 405) of the vertical transistors, and a gate region adjacent to the channel region of the vertical transistor is occupied by a portion of the continuous word line (FIG. 1, 38-40; para. 35, 58-61, 85-86). Shih teaches gate line structures formed as the integrated portions of the word line which are adjacent to the channel region of a vertical transistor. Shih further teaches forming continuous word lines in the same plane as the channel structure as a simple processing method, which has a limited number of deposition and etching steps, for forming a pair of word lines adjacently coupled to channel regions of vertical transistors (para. 109-111, 2). The combination of Hua and Shih teaches that the gate line structure of Hua can be a portion of a continuous word line formed by a simple processing method. The combination of Hua and Shih teaches word lines coupled to the memory cells (Hua - para. n0034); and word line dielectric layers (Hua – annotated FIG. 34a: el. line structure dielectric layer| annotated FIG. 34a provided in Re claim 1 section), wherein each two adjacent word lines are in direct contact with a corresponding word line dielectric layer (Hua – annotated FIG. 34a: el. line structure dielectric layer, line 1, line 2| annotated FIG. 34a provided in Rec claim 1 section).
It would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Hua and Shih, to enable using the continuous word line adjacent to a channel region of Shih in the memory device of Hua, for the benefit of simplifying a manufacturing process by utilizing a known method for efficiently integrating a word line into a vertical transistor semiconductor device.
The combination of Hua and Shih fails to teach a memory system comprising: a memory controller coupled to the memory device.
In a similar field of endeavor, Kim teaches a memory device (para. 128) comprising a plurality of memory cells, wherein the memory cells comprise vertical transistors (para. 28-29), and a memory system (FIG. 29: el. 600; para. 123) comprising: a memory device (para. 128; FIG. 29: el. 610 or 630) and a memory controller (FIG. 29: el. 620; para. 123) coupled to the memory device (FIG. 29; para. 125). Kim further teaches a benefit of utilizing a memory controller with the memory device is to control data input and output operations for the memory device to enable the operational use of the memory device (para. 0011).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of the combination of Hua and Shih with the teachings of Kim, to enable using the memory controller and its coupling to a memory device of Kim in the memory system comprising a memory device of the combination of Hua and Shih, for the benefit of controlling data input and output operations for the memory device to enable operational use of the memory device.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEVIN GOODLING whose telephone number is (571)272-2552. The examiner can normally be reached M-F 7:30am - 5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/D.G./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
