Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/25/2025 has been entered.
Claim Objections
Claim 18 is objected to because of the following informalities: claim 18 concludes with two periods. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites the limitation “the first processor to execute a flash translation layer to predetermine open contiguous blocks on the memory device where sequential host data is to be written and provide a beginning address of the open contiguous blocks to another auxiliary processor for the other auxiliary processor to populate an address translation table with logical-to-physical mappings starting at the beginning address with an offset, where each entry in the address translation table corresponds to a fixed granularity, wherein functions of the auxiliary processor are separate from functions of the flash translation layer.”
Claim 10 recites the limitation “prior to transmitting the sequential host data to the memory device, populating, by the auxiliary processor, an address translation table with logical-to-physical mappings starting at the beginning address with an offset, where each entry in the address translation table corresponds to a fixed granularity, wherein functions of the auxiliary processor are separate from functions of a flash translation layer executed by the first processor.”
Claim 18 recites the limitation “an auxiliary processor to receive the beginning address and populate an address translation table with logical-to-physical mappings starting at the beginning address with an offset, where each entry in the address translation table corresponds to a fixed granularity, wherein functions of the auxiliary processor are separate from functions of the flash translation layer.”
While there is discussion of host interface module 112/auxiliary processor and flash translation layer 116, there is no clear teaching of a flash translation layer providing a beginning address to another auxiliary processor. Paragraph 0016 discloses that controller 108 may include a host interface module 112 and a flash translation layer 116. Paragraphs 0022-0032 discuss communication between HIM 112 and flash translation layer 116, but do not discuss any separation between their functions. Paragraph 0038 discussing figure 4 discusses an environment where there are a plurality of controllers 108, each having HIM 112 and a flash translation layer 116, but there is no discussion of a HIM 112 on one controller 108 communicating with a flash translation layer 116 on a different controller 108.
The application as originally filed makes no mention as to the functions of an auxiliary processor being separate from functions of the flash translation layer. There is no clear discussion of what functions would be separate, or what it means for functions to be separate. Accordingly, the specification as originally filed does not show that, as of the earliest effective filing date sought, applicant had possession of the claimed invention.
Claims 2-9, 11-17, 19, and 20 depend from claims 1, 10, and 18, and are rejected for the same reasons as claims 2-9, 11-17, 19, and 20.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 recites the limitation "another auxiliary processor" and “the other auxiliary processor” in line 12. There is insufficient antecedent basis for this limitation in the claim as there is no previous recitation of an auxiliary processor to provide antecedent basis for there being another auxiliary processor. Additionally, it is unclear if “the other auxiliary processor” refers to the recited “another auxiliary processor” or a different processor.
Claim 1 recites the limitation "the auxiliary processor" in lines 15-16. There is insufficient antecedent basis for this limitation in the claim as it is unclear if it refers to the previously recited “another auxiliary processor,” “the other auxiliary processor,” or some other auxiliary processor.
Claim 1 recites “functions of the auxiliary processor” and “functions of the flash translation layer” however, there is no previous recitation of an auxiliary processor or the flash translation layer having anything identified as functions. Accordingly, it unclear as to what functions are separate.
Claims 1 recites that “functions of the auxiliary processor are separate from functions of the flash translation layer. However, functions are not physical things. It is unclear what it means for functions to be separate, and the specification does not provide guidance as to the meaning of the term.
Claim 10 recites “another auxiliary processor” in lines 3. There is insufficient antecedent basis for this limitation in the claim as there is no previous recitation of an auxiliary processor to provide antecedent basis for there being another auxiliary processor.
Claim 10 recites “the auxiliary processor” in lines 12-13 and line 15. There is insufficient antecedent basis for this limitation in the claim, as claim 10 refers to “another auxiliary processor.” It is unclear if “the auxiliary processor” refers to the recited “another auxiliary processor” or an unrecited auxiliary processor that would provide antecedent basis for identifying an entity as “another auxiliary processor.
Claims 10 recites that “functions of the auxiliary processor are separate from functions of a flash translation layer executed by the first processor. However, functions are not physical things. It is unclear what it means for functions to be separate, and the specification does not provide guidance as to the meaning of the term.
Claim 18 recites “functions of the auxiliary processor are separate from functions of a flash translation layer. However, functions are not physical things. It is unclear what it means for functions to be separate, and the specification does not provide guidance as to the meaning of the term.
Claims 2-9, 11-17, 19, and 20 depend from claims 1, 10, and 18, and are rejected for the same reasons as claims 2-9, 11-17, 19, and 20.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Muthiah (US 2023/0409470) in view of Hanna (US 2023/0367718) in view of Nakanishi et al. (US 2010/0005227).
Regarding independent claim 1, Muthiah teaches a storage device (figure 1, item 102) communicatively coupled to a host device (figure 1, item 104) that transmits write commands to store data on a memory device (paragraph 0033),
the storage device comprising: a memory device to store data (figure 1, NVM 110);
a first processor (figure 1, item 123, Figure 9, item 902) to execute a host interface module to interface with the host device and receive, from the host device, a command to store host data on the memory device (paragraph 0107 shows that controller 902 includes command module 908 which receives commands from a host, and performs steps 810 and 816 of figure 8. See paragraphs 0089 and 0096 showing commands are from a host.)
classify the host data as one of sequential host data and random host data; Paragraph 0024 shows that the controller may store sequential data in blocks allocated for sequential data and random data to other blocks allocated for random data.
and the first processor to execute a flash translation layer to [allocate] blocks on the memory device (Paragraph 0106 shows allocation module 906 performs blocks 802 and 804 of figure 8, which include allocating regions of NVM for a host and looks up physical addresses of blocks that have no entries (i.e. are open). Paragraph 0046 shows that space is allocated in a memory location for data received from the host, and then is stored in the allocated memory location. Paragraph 0047 shows that the functions of the controller may be implemented by one or more processors.)
and provide a beginning address of the [memory location] to another auxiliary processor for the other auxiliary processor to populate an address translation table with logical-to-physical mappings starting at the beginning address with an offset (paragraph 0046 shows that the L2P mapping table is updated when data is stored in the volatile memory 118. Paragraph 0039 shows that the L2P table stores the block (beginning address) and an offset at which data associated with an LBA is stored. Paragraph 0108 shows that controller 902 may include storage module (which performs steps 812, 818, and 820 of figure 8) that identifies from the L2P mapping updates a physical address associated with the logical address, stores data in the memory and updates the L2P mapping table)
wherein functions of the auxiliary processor are separate from functions of the flash translation layer. (The functions of allocation module 906 and storage module 910 are separate in that they are separate steps of method 800. Additionally, paragraph 0047 shows that the functions of the controller may be implemented by one or more processors.
Muthiah does not expressly teach that the flash translation layer is to predetermine open contiguous blocks on the memory device where sequential host data is to be written, and provide a beginning address of the open contiguous blocks to another auxiliary processor ,where each entry in the address translation table corresponds to a fixed granularity.
HANNA discloses a storage device (memory system 110) communicatively coupled to a host device (host system 105) that transmits write commands to store data on a memory device ([0014-0017] FIG. 1 "The host system 105 may use the memory system 110, for example, to write data to the memory system 110"), the storage device comprising:
a memory device to store data ([0015] "A memory system 110 may be or include any device or collection of devices, where the device or collection of devices includes at least one memory array"); and
([0022] "The memory system controller 115 may include hardware such as one or more integrated circuits... The memory system controller 115 may be or include a microcontroller" and [0011] "flash translation layer (FTL) of the memory device". [0076] FIGs. 1 and 5 “process flow 500 may be performed by a controller of a memory system or a memory device (or both) such as a memory system controller 115 or a local controller 135.” Controller 115 or local controller 135 may be any multiple processors executing host interface or flash translation layer),
A first processor to execute a host interface module to interface with the host device and receive, from the host device, a command to store host data on the memory device ([0078-0079] "At 505, a command associated with data having corresponding set of logical address may be received... At 510, a subset of logical addresses of the set of logical addresses may be evaluated as to whether it is sequential". [0022] "The memory system controller 115 may include hardware such as one or more integrated circuits... The memory system controller 115 may be or include a microcontroller" and [0011] "flash translation layer (FTL) of the memory device". [0076] FIGs. 1 and 5 “process flow 500 may be performed by a controller of a memory system or a memory device (or both) such as a memory system controller 115 or a local controller 135.” Controller 115 or local controller 135 may be any multiple processors executing host interface or flash translation layer)
classify the host data as one of sequential host data and random host data ([0011-0012] "The mapping information may include multiple levels for storing entries... For example, a macro level (e.g., a macro map) may be used to store coarser entries if logical addresses are sequential"); and
the first processor to execute a flash translation layer to provide a beginning address of the open contiguous blocks to another auxiliary processor ([0035] "The memory system may generate and store a set of compressed entries in a macro level of the mapping information" [0072-0073] "The global level may include pointers to where data is mapped in the macro level or in the L2P level". [0022] "The memory system controller 115 may include hardware such as one or more integrated circuits... The memory system controller 115 may be or include a microcontroller" and [0011] "flash translation layer (FTL) of the memory device". [0076] FIGs. 1 and 5 “process flow 500 may be performed by a controller of a memory system or a memory device (or both) such as a memory system controller 115 or a local controller 135.” Controller 115 or local controller 135 may be any multiple processors executing host interface or flash translation layer)
for the other auxiliary processor to populate an address translation table with logical-to-physical mappings starting at the beginning address with an offset ([0011] "The memory system may generate and maintain mapping information (e.g., a logical to physical (L2P) table) at, for example, a flash translation layer (FTL) of the memory device". [0022] "The memory system controller 115 may include hardware such as one or more integrated circuits... The memory system controller 115 may be or include a microcontroller" and [0011] "flash translation layer (FTL) of the memory device". [0076] FIGs. 1 and 5 “process flow 500 may be performed by a controller of a memory system or a memory device (or both) such as a memory system controller 115 or a local controller 135.” Controller 115 or local controller 135 may be any multiple processors executing host interface or flash translation layer),
where each entry in the address translation table corresponds to a fixed granularity ([0036 shows that the L2P level tables are fixed granularity, while the macro level may be coalesced into a single entry.)
Before the earliest effective filing date of the invention, it would have been obvious to combine the mapping table of Hanna with the system of Muthiah.
The motivation for doing so would have been to reduce latency associated with access operations, Hanna paragraphs 0011 and 0012.
The combination of Muthiah and HANNA does not explicitly disclose a flash translation layer to predetermine open contiguous blocks on the memory device where sequential host data is to be written.
However, NAKANISHI discloses a flash translation layer to predetermine open contiguous blocks on the memory device where sequential host data is to be written ([0089] FIG. 8A The empty capacity detector 260 detects an empty capacity sequentially from a first physical block in the region 1 of the nonvolatile memory 210 on the basis of the physical region management table).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify HANNA’s storage device to further include a flash translation layer to predetermine open contiguous blocks on the memory device where sequential host data is to be written, to allow the nonvolatile memory device to quickly start the writing of data (see NAKANISHI [0009]).
Regarding dependent claim 2, HANNA discloses wherein while the flash translation layer transmits the sequential host data to be written to the memory device and the flash translation layer determines that the address translation table is populated, the first processor executes the flash translation layer to perform an update to the address translation table and complete processing for the command ([0082-0083] "The memory system may determine whether one or more logical addresses of the subset are sequential... store an entry in a second level of the mapping information").
Regarding dependent claim 3, HANNA discloses wherein while the flash translation layer transmits the sequential host data to be written to the memory device and the flash translation layer determines that the address translation table is not populated, the first processor executes the flash translation layer to perform the logical-to-physical mappings, populate the address translation table, and complete processing for the command ([0083-0084] "If the subset of logical addresses is sequential... generate the set of entries" for writing data).
Regarding dependent claim 4, HANNA does not explicitly disclose wherein the first processor executes the flash translation layer provide the beginning address and an ending address of the open contiguous blocks to the auxiliary processor and the auxiliary processor uses the beginning address and the ending address to determine a size of the open contiguous blocks.
However, NAKANISHI discloses wherein the first processor executes the flash translation layer provide the beginning address and an ending address of the open contiguous blocks to the auxiliary processor and the auxiliary processor uses the beginning address and the ending address to determine a size of the open contiguous blocks ([0080]-[0090] FIG. 8A the read and write controller 240 contains the memory map (with the maintained empty block addresses, and communicates with the empty capacity parameter notification part 250. The empty capacity detector 260 detects an empty capacity sequentially from a first physical block in the region 1 of the nonvolatile memory 210 on the basis of the physical region management table. Empty capacity parameter includes determined size).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify HANNA’s storage device to further include a flash translation layer provides the beginning address and an ending address of the open contiguous blocks to the host interface module and the host interface module uses the beginning address and the ending address to determine a size of the open contiguous blocks, to allow the nonvolatile memory device to quickly start the writing of data (see NAKANISHI [0009]).
Regarding dependent claim 5, HANNA does not explicitly disclose wherein the auxiliary processor does not populate the address translation table if the host interface module determines that remaining space available in the open contiguous blocks is smaller than the size of the sequential host data.
However, NAKANISHI discloses wherein the auxiliary processor does not populate the address translation table if the host interface module determines that remaining space available in the open contiguous blocks is smaller than the size of the sequential host data ([0104] FIG. 13 the application 120 judges whether or not the empty capacity is sufficient for recording the file data (S205). If not sufficient, then not recordable).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify HANNA’s storage device to further include the auxiliary processor does not populate the address translation table if the host interface module determines that remaining space available in the open contiguous blocks is smaller than the size of the sequential host data, to allow the nonvolatile memory device to quickly start the writing of data (see NAKANISHI [0009]).
Regarding dependent claim 6, HANNA discloses wherein the first processor executes the host interface module to send a message to the flash translation layer and the first processor executes the flash translation layer to update the beginning address, and wherein the auxiliary processor populates the address translation table using an updated beginning address ([0074] "The memory system may update one or more global entries in the global level to include pointers to the data stored in the L2P level").
Regarding dependent claim 7, HANNA discloses wherein the auxiliary processor does not populate the address translation table if the host interface module determines that the host data is the random host data ([0079-0080] "If the subset of logical addresses is not sequential... store a set of entries in the first level", i.e. stops populating the address translation table/map).
Regarding dependent claim 8, HANNA discloses wherein entries in the address translation table are updated at the fixed granularity ([0030] "For some NAND architectures, memory cells may be read and programmed at a first level of granularity").
Regarding dependent claim 9, HANNA discloses wherein the logical-to-physical mappings map logical addresses associated with the sequential host data to physical addresses in the memory device ([0011] "The mapping information may include a mapping between the logical addresses associated with the data and the physical addresses of the memory cells").
Regarding independent claims 10 and 18, the applicant is directed to the rejection to claim 1 set forth above, as they are rejected based on the same rationale.
Regarding dependent claims 11 and 19, the applicant is directed to the rejection to claim 2 set forth above, as they are rejected based on the same rationale.
Regarding dependent claims 12 and 20, the applicant is directed to the rejection to claim 3 set forth above, as they are rejected based on the same rationale.
Regarding dependent claim 13, the applicant is directed to the rejection to claim 4 set forth above, as it is rejected based on the same rationale.
Regarding dependent claim 14, the applicant is directed to the rejection to claim 5 set forth above, as it is rejected based on the same rationale.
Regarding dependent claim 15, the applicant is directed to the rejection to claim 6 set forth above, as it is rejected based on the same rationale.
Regarding dependent claim 16, the applicant is directed to the rejection to claim 7 set forth above, as it is rejected based on the same rationale.
Regarding dependent claim 17, the applicant is directed to the rejection to claim 8 set forth above, as it is rejected based on the same rationale.
Response to Arguments
Applicant’s arguments, see page 9 of the response filed 11/25/2025, with respect to the rejections of claims 1-20 under 35 USC 112(b) have been fully considered and are persuasive. The rejections of claims 1-20 under 35 USC 112(b) has been withdrawn.
Applicant’s arguments, see pages 9-12 of the response filed 11/25/2025, with respect to the rejection(s) of claim(s) 1-20 under 35 USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Muthiah.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jared Ian Rutz whose telephone number is (571)272-5535. The examiner can normally be reached Monday-Friday, 8:00 AM to 4:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, John Cottingham can be reached at (571)272-1400. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135