Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
In Paragraph [0006], "a conventional mechanical LiDAR sensor physically rotate a sensor" should read "a conventional mechanical LiDAR sensor physically rotates a sensor"
In Paragraph [0022], "a light activation signal RON" should read "a light activation signal LON"
In Paragraph [0036], "the histogram counter 300" should read "the histogram counter 400"
In Paragraph [0048], "a corresponding flip-flip 211" should read "a corresponding flip-flop 211"
In Paragraph [0057], "the second TDC circuit 230" should read "the second TDC circuit 220"
In Paragraph [0104], "the trigger signal TRIG is enable" should read "the trigger signal TRIG is enabled".
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the trigger signal" in Line 13. There is insufficient antecedent basis for this limitation in the claim. This limitation is unclear as there are two previous mentions of “a trigger signal” in Line 11 and Lines 11-12 that have not been distinguished. The second mention of “a trigger signal” should be clarified if it is the same as the first or a new separate trigger signal.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Meynants (EP 3474038 A1) in view of Xie et al. (CN 117434521 A).
Regarding Claim 1, Meynants teaches:
A ranging device ([0001]: “This invention relates to an image sensor…and the method relate[d] to time-of-flight 3D imaging capabilities”) comprising:
a sensor array including a plurality of sensors ([0014]: “In some embodiments a global shutter CMOS image sensor can be used including an array of pixels”) each sensing reflected light from object irradiated by a light source ([0088]: “the emitter EM creates a set of light pulses. These emitted light pulses eventually are reflected by an external object and traverse back to the image sensor IS. The reflected light pulses are collected by the pixels”);
a row driver configured to control the sensor array row by row to output a plurality of trigger signals ([0018]: “the image sensor may drive a limited amount of pixels, e.g. a limited number or subset of rows”).
Meynants does not teach, but Xie teaches:
A ranging device comprising ([0001]: “The invention belongs to the technical field of sensors, and it particularly relates to a DTOF [direct time of flight] sensor, a ranging method, a laser receiving module and a ranging device.”):
a time detection circuit configured to detect time interval when reflected light arrives at the plurality of sensors after the object is irradiated by using the plurality of trigger signals ([0059]: “the laser emitting module 110 emits laser pulses to a target scene, the light pulses reflected by the target scene are incident on the SPAD photosensitive pixels…voltage pulse signals with fixed pulse width and amplitude are output to M TDCs with different resolutions”),
wherein the time detection circuit performs a first operation to detect a window period where a trigger signal is activated by using a trigger signal and a first clock signal ([0006]: “During distance measurement, a coarse histogram with coarse time resolution is generated by a coarse resolution TDC and histogram circuit”), and performs a second operation to detect a section where the trigger signal is activated among a plurality of sections that divides the window period by using a second clock signal having smaller period than a period of the first clock signal ([0017]: “After determining the coarse time interval position of the object to be measured in a wide range, generating a fine histogram with a fine time resolution in a time range corresponding to the coarse phase through a fine resolution TDC and a histogram circuit”).
It would have been obvious to one of ordinary skill in the art to modify the ranging device of Meynants with a more optimal time-detection circuit as taught by Xie based on two clock signals of different periods with a reasonable expectation of success. This would have the predictable result of improving timing precision and efficiency in determining time-of-flight of the emitted light from the row-driven sensor array by performing a first operation with a longer period clock (coarse resolution TDC) and a second operation with a shorter period clock (fine resolution TDC).
Regarding Claim 16, which depends from rejected Claim 1, Meynants further teaches:
The ranging device of claim 1, wherein the sensor includes:
a plurality of light receiving elements configured to generate output signals after receiving the reflected light respectively ([0088]: “the emitter EM creates a set of light pulses. These emitted light pulses eventually are reflected by an external object and traverse back to the image sensor IS”I; [0089]: “After exposure, i.e. when the exposure time Texp has lapsed, a time-of-flight signal has been accumulated”);
a plurality of analog front end circuit configured to generate pulse signals according to the output signals of the plurality of light receiving elements respectively ([0059]: “the image sensor can be connected to a configurable analog frontend with a programmable gain amplifier PGA and a sample and hold circuit S/H”; Figure 1); and
a trigger signal generating circuit configured to generate a trigger signal according to the plurality of pulse signals ([0022]: “an emitter is configured to emit a plurality of light pulses in response to respective trigger pulses of an emitter control signal”).
Claims 2-7 and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Meynants in view of Xie as applied to Claim 1 above, and further in view of Sharma et al. (US 20170052065 A1).
Regarding Claim 2, which depends from rejected Claim 1, Meynants and Xie teach:
The ranging device of claim 1, wherein the time detection circuit comprises:
a peak detection circuit configured to perform a first peak detection operation to detect a peak in a first histogram stored in the histogram counter during the first operation ([0069-71]: “the digital processing circuit 50 can determine the time of flight directly according to the histogram data or determine the time of flight and distance information by the external device, wherein, the time of flight is: [(K1-1) *T1/m1 + (K2-1) *T2/m2 + ... + (KM-1-1) *TM-1/mM-1 + KM* TM/mM]; wherein K1, K2 to KM respectively represent the position of the time interval corresponding to the maximum counting peak value in the histogram data of the first histogram circuit”), and to perform a second peak detection operation to detect a peak in a second histogram stored in the histogram counter during the second operation ([0072]: “after determining the time unit width position of the object to be measured within a large range, determining the time unit width position of the maximum peak value in the second histogram data”); and
a peak storage memory storing information on location of a detected peak ([0075]: “a digital code is generated and transmitted to the second histogram circuit 42, and the second histogram circuit 42 is equivalent to a fine histogram circuit, which contains y memory cells”).
Meynants and Xie do not teach, whereas Sharma teaches:
a histogram counter including a plurality of first counters where one of the plurality of first counters is activated according to a plurality of activation signals and an activated first counter counts the trigger signal ([0030]: “In each frame, each of processing circuits 42 counts photons that are incident on the corresponding sensing element 40 in a plurality of different time bins and constructs a histogram of the respective counts over the different time bins”);
a time-to-digital converter (TDC) circuit configured to generate time difference information according to the second operation ([0025]: “During the fine measurement phase, the memory of each pixel stores respective counts of the photons that arrive at the sensing element in multiple different time bins, which span the detection window that the controller set for this pixel. At the conclusion of the frame, the controller processes the histogram of the respective counts stored in the pixel memory in order to derive and output the respective time-of-arrival value for the corresponding sensing element”) and a plurality of shift signals generated according to the first operation, and to generate the plurality of activation signals according to a plurality of decoding signals ([0032]: “Processing circuit 42 comprises a gating signal generator 56, which comprises, in the present example, a shift register 58, such as an eight-bit shift register, with a multiplexer 60 to produce output pulses at the time within each acquisition interval that is indicated by the shift register value”);
a decoder configured to generate the plurality of decoding signals by decoding the time difference information ([0032]: “Alternatively, gating signal generator 56 may comprise a counter and decoder”).
It would have been obvious to one of ordinary skill in the art to modify the ranging device of Meynants and the more optimal time-detection circuit based on a coarse and fine clock as taught by Xie together with the histogram counter, the TDC circuit, and the decoder as taught by Sharma with a reasonable expectation of success. The additional components taught by Sharma are known in the art for analog-to-digital time conversion and incorporating them would have the predictable result of improving timing precision and efficiency in determining time-of-flight of the emitted light in a ranging device.
Regarding Claim 3, which depends from rejected Claim 2, Sharma further teaches:
The ranging device of claim 2, wherein the TDC circuit includes:
a first TDC circuit configured to generate a plurality of shift signals sequentially activated after a start signal according to the first clock signal ([0032]: “Processing circuit 42 for each sensing element 40 comprises logic circuits that provide the necessary timing signals to sensing element 40 (SPAD EN) and process the pulses output by SPAD 52 (SPAD OUT). Processing circuit 42 comprises a gating signal generator 56, which comprises, in the present example, a shift register 58, such as an eight-bit shift register, with a multiplexer 60 to produce output pulses at the time within each acquisition interval that is indicated by the shift register value”);
a window generating circuit configured to generate a window signal identifying a window period corresponding to a peak detected during the first operation according to the first clock signal ([0032-0033]: “A sub-window manager circuit 62 controls the settings of gating signal generator 56 under the command of a pixel controller 72… controller 72 identifies the optimal detection window for this pixel 50. Controller 72 then instructs circuit 62 to set the gating interval for the fine measurement interval, which will occupy the remainder of the frame, to coincide with this detection window”);
a second TDC circuit configured to generate the time difference information corresponding to time between beginning of the window period ([0033]: “Controller 72 then instructs circuit 62 to set the gating interval for the fine measurement interval, which will occupy the remainder of the frame, to coincide with this detection window”) and the trigger signal according to the second clock signal ([0034]: “A phase detector 64 receives pulses that are output by SPAD 52 in response to the incident photons during each gating interval, and measures the pulse timing relative to a clock signal…thus function as a time-to-digital converter (TDC), converting the arrival time of pulses from SPAD 52 within the detection window to corresponding count values in memory 70.”); and
a selection circuit configured to provide the plurality of shift signals as the plurality of activation signals during the first operation and to provide the plurality of decoding signals as the plurality of activation signals during the second operation ([0032]: “Processing circuit 42 comprises a gating signal generator 56, which comprises, in the present example, a shift register 58, such as an eight-bit shift register, with a multiplexer 60 to produce output pulses at the time within each acquisition interval that is indicated by the shift register value”).
Regarding Claim 4, which depends from rejected Claim 3, Sharma further teaches:
The ranging device of claim 3, wherein the second TDC circuit includes:
a second counter configured to count the second clock signal while the window signal is activated ([0034]: “Following each pulse from SPAD 52, an incrementer 68 converts the pulse timing output provided by detector 64 to an address in a histogram memory 70 and increments the count value at this address in the memory”); and
a phase encoder configured to generate a phase signal by sampling a plurality of multi-phase second clock signals having different phases from the second clock signal according to the trigger signal after the window signal is activated ([0034]: “A phase detector 64 receives pulses that are output by SPAD 52 in response to the incident photons during each gating interval, and measures the pulse timing relative to a clock signal provided by a clock generator 66 (which typically serves the entire processing chip 38). To provide the desired sub-nanosecond resolution, the clock signal may comprises multiple phases, for example, eight phases, on respective input lines to phase detector”),
wherein the decoder generates the plurality of decoding signals by decoding an output of the second counter and an output of the phase encoder ([0034]: “Phase detector 64 and incrementer 68 thus function as a time-to-digital converter (TDC), converting the arrival time of pulses from SPAD 52 within the detection window to corresponding count values in memory 70”).
Regarding Claim 5, which depends from rejected Claim 2, Xie further teaches:
The ranging device of claim 2, wherein the peak detection circuit includes:
a predetermined number of first registers ([0075]: “wherein the first histogram circuit 41 is equivalent to a coarse histogram circuit, and the coarse histogram circuit comprises x storage units”);
a predetermined number of second registers ([0075]: “the second histogram circuit 42 is equivalent to a fine histogram circuit, which contains y memory cells”); and
a control circuit configured to compare a value of one of the predetermined number of first registers and a value of one of the predetermined number of second registers and to store values of the predetermined number of first registers into the predetermined number of second registers ([0055]: “m histogram circuits 40 connected with the M TDCs with different resolutions one by one respectively, wherein each histogram circuit comprises a preset number of storage units, the preset number of storage units are used for respectively counting digital codes corresponding to the preset number of phase intervals and converting the digital codes into corresponding histogram data, and each histogram data is processed by the digital processing circuit 50, transmitted to the interface circuit 60 and output to external equipment through the interface circuit 60”).
6
Regarding Claim 6, which depends from rejected Claim 5, Sharma further teaches:
The ranging device of claim 5, wherein when all of counter values of the histogram counter are compared during the first operation ([0041]: “at the conclusion of [coarse measurement] phase 92, memory 70 will contain a histogram of pulse arrival counts per gating interval. Pixel controller 72 processes this histogram in order to identify the gating interval in which SPAD 52 actually received reflected laser pulses…if for a single group 100 of acquisition periods 98 (or possibly two adjacent groups), the count in the corresponding histogram bin is significantly higher than a baseline count averaged over the other bins”), the control circuit stores a predetermined counter address corresponding to values of the predetermined number of second registers in the peak storage memory ([0042]: “the controller identifies this gating interval as the detection window for pixel 50…Controller 72 instructs sub-window manager 62 to fix the gating interval for pixel 50 to coincide with this detection window for the duration of a fine measurement phase 94, at a window-fixing step”).
Regarding Claim 7, which depends from rejected Claim 6, Sharma further teaches:
The ranging device of claim 6, wherein the control circuit separately stores a selected number of counter addresses among the predetermined number of counter addresses in the peak storage memory, and the window generating circuit generates the window signal referring to the selected number of counter addresses ([0042]: “the controller identifies this gating interval as the detection window for pixel 50…Controller 72 instructs sub-window manager 62 to fix the gating interval for pixel 50 to coincide with this detection window for the duration of a fine measurement phase 94, at a window-fixing step”).
Regarding Claim 11, which depends from rejected Claim 5, Sharma further teaches:
The ranging device of claim 5, wherein the peak detection circuit performs the first peak detection operation multiple times, and the peak detection circuit resets counter values corresponding to the predetermined number of first counters of the histogram counter when the first peak detection operation is terminated ([0039]: “The method of FIGS. 3 and 4 is typically performed repetitively over a series of image frames…(In general, however, only a part of each acquisition period is actually used for pulse acquisition…and the remainder of the acquisition period can be used for reset, control and processing.)”).
Regarding Claim 12, which depends from rejected Claim 11, Sharma further teaches:
The ranging device of claim 11, wherein when a plurality of window periods are detected during the first operation, the decoder divides a plurality of first counters in the histogram counter into a plurality of groups corresponding to a number of detected window periods, and generates the decoding signal so that one window corresponds to one group ([0042]: “When significant counts are collected in two adjacent gating intervals during coarse measurement phase 92, controller 72 can set the detection window to an intermediate time delay, between the two gating intervals”).
Regarding Claim 13, which depends from rejected Claim 5, Sharma further teaches:
The ranging device of claim 5, wherein when a value of a peak detected in the first peak detection operation is smaller than a threshold value, the peak detection circuit ignores result of the first peak detection operation ([0041]: “Controller 72 considers acquisition in phase 92 to have been successful if…the count in the corresponding histogram bin is significantly higher than a baseline count averaged over the other bins. If no such dominant bin is found in the histogram in memory 70 at step 84, controller 72 may instruct sub-window manager 62 to return to step 82 and perform a further sweep. Alternatively, controller 72 may output a null TOF value for the pixel in question in this frame”).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Meynants in view of Xie and Sharma as applied to Claim 5 above, and further in view of Henderson et al. (WO 2022055833 A1).
Regarding Claim 8, which depends from rejected Claim 5, Meynants, Xie, and Sharma do not teach, whereas Henderson teaches:
The ranging device of claim 5, wherein a plurality of counters in the histogram counter and the predetermined number of first registers are connected to form a ring, and the peak detection circuit performs the peak detection operation by shifting the values in the ring until values of the histogram counter are recovered to original values ([0027]: “the logic-based counter circuit may include a linear feedback shift register that is configured to execute the increment operation by sequentially shifting the data stored in the storage element of the respective one of the memory cells to a bit line of a succeeding one of the memory cells in the row using a linear feedback loop”).
It would have been obvious to one of ordinary skill in the art to modify the ranging device of Meynants and the more optimal time-detection circuit based on a coarse and fine clock as taught by Xie and the histogram counter, the TDC circuit, and the decoder as taught by Sharma together with the shift register ring counter as taught by Henderson with a reasonable expectation of success. This type of ring counter as taught by Henderson is known in the art for digital logic applications, particularly for peak detection of histograms and incorporating this would have the predictable result of allowing for effectively determining time-of-flight of the emitted light in a ranging device.
Claims 9, 10, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Meynants in view of Xie, Sharma, and Henderson as applied to claim 8 above, and further in view of Nakada (US 20240255622 A1).
Regarding Claim 9, which depends from rejected Claim 8, Meynants, Xie, Sharma, and Henderson do not teach, whereas Nakada teaches:
The ranging device of claim 8, wherein the time detection circuit further includes a filter configured to filter a value output from the histogram counter to output a filtered value ([0085]: “The filter processing section 23 (FIG. 1 ) is configured to perform filter processing on each of the plurality of histograms H1 to generate each of a plurality of histograms H2”), and
wherein the histogram counter, the filter, and the predetermined number of first registers are connected to form the ring, and the peak detection circuit performs the peak detection operation by shifting the values in the ring until values of the histogram counter are recovered to original values ([0086]: “The filter processing section 23 includes a shift register 31, a multiplying part 32, a maximum value detection part 33, a removing part 34, and an adding part 35”; Figure 6).
It would have been obvious to one of ordinary skill in the art to modify the ranging device of Meynants and the more optimal time-detection circuit based on a coarse and fine clock as taught by Xie and the histogram counter, the TDC circuit, and the decoder as taught by Sharma and the circular shift register as taught by Henderson together with the filter as taught by Nakada with a reasonable expectation of success. This type of filter as taught by Nakada is known in the art for digital logic applications, particularly for smoothing histogram outputs and incorporating this would have the predictable result of allowing for effectively determining time-of-flight of the emitted light in a ranging device.
Regarding Claim 10, which depends from rejected Claim 9, Nakada further teaches:
The ranging device of claim 9, wherein the filter includes:
a plurality of filter registers configured to sequentially shift and store an output of the histogram counter;
a plurality of multiplication circuits configured to multiply outputs of the plurality of filter registers with a plurality of coefficients respectively; and
and adder circuit configured to add outputs of the plurality of multiplication circuits. ([0086]: “The filter processing section 23 includes a shift register 31, a multiplying part 32, a maximum value detection part 33, a removing part 34, and an adding part 35”; Figure 6).
Regarding Claim 14, which depends from rejected Claim 5, Nakada further teaches:
The ranging device of claim 5, wherein when a value of a peak detected in the first peak detection operation corresponds to a distance longer than a threshold distance, the peak detection circuit ignores result of the first peak detection operation ([0122]: “the filter processing section 23 excludes a maximum value detected by the maximum value detection part 33 from targets that are subject to the filter processing to reduce a component in accordance with the interference light in a histogram”).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Meynants in view of Xie, and Sharma as applied to Claim 5 above, and further in view of Pacala et al. (US 12189038 B2).
Regarding Claim 15, which depends from rejected Claim 5, Meynants, Xie, and Sharma do not teach, whereas Pacala teaches:
The ranging device of claim 5, wherein the control circuit compares a value of a selected first register of the predetermined number of first registers with a value of a corresponding second register and stores values of the predetermined number of first registers in the predetermined number of second registers during the second peak detection operation ([12]: “accumulating photon counts from the one or more photodetectors into a plurality of first registers to represent a histogram of photon counts”; “further include identifying a plurality of peaks in the histogram in the plurality of first registers through a plurality of executions of a peak detection circuit”; [13]: “a plurality of second registers configured to store the plurality of peaks identified by the peak detection circuit”), and
wherein the control circuit accumulates values of the histogram counter in one or more first registers among the predetermined number registers except the selected first register ([13]: “peaks identified as maximum peaks during previous executions of the peak detection circuit may be excluded from being identified as maximum peaks during subsequent executions of the peak detection circuit by masking registers in the plurality of first registers that represent the peaks previously identified as maximum peaks from the peak detection circuit during subsequent executions”).
It would have been obvious to one of ordinary skill in the art to modify the ranging device of Meynants and the more optimal time-detection circuit based on a coarse and fine clock as taught by Xie and the histogram counter, the TDC circuit, and the decoder as taught by Sharma together with the plurality of registers as taught by Pacala with a reasonable expectation of success. Utilizing multiple registers for multiple peak detection operations is known in the art for time-to-digital conversion applications, particularly for using one register for binned counts of a histogram and another for peak storage, and incorporating this would have the predictable result of allowing for effectively determining time-of-flight of the emitted light in a ranging device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN C NATHAN whose telephone number is (571)270-0331. The examiner can normally be reached 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Isam Alsomiri can be reached at (571) 272-6970. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KEVIN CHRISTOPHER NATHAN/Examiner, Art Unit 3645
/ISAM A ALSOMIRI/Supervisory Patent Examiner, Art Unit 3645
Prosecution Insights